STA505
40V 3.5A QUAD POWER HALF BRIDGE
1
■
■
FEATURES
MULTIPOWER BCD TECHNOLOGY
MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
200mΩ R
dsON
COMPLEMENTARY DMOS
OUTPUT STAGE
CMOS COMPATIBLE LOGIC INPUTS
THERMAL PROTECTION
THERMAL WARNING OUTPUT
UNDER VOLTAGE PROTECTION
Figure 1. Package
PowerSO36
■
Table 1. Order Codes
Part Number
STA505
STA50513TR
Package
PowerSO36
in Tape & Reel
■
■
■
■
current capability.
2
DESCRIPTION
STA505 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology. The device can be used as
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
capability, and as half bridge (Binary mode) with half
The device is particularly designed to make the out-
put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 50 + 50W @
THD = 10% at V
cc
30V output power on 8Ω load and
80W @ THD = 10% at V
cc
36V on 8Ω load in single
BTL configuration. The input pins have threshold pro-
portional to V
L
pin voltage.
Figure 2. Audio Application Circuit (Dual BTL)Pin Description
V
CC
1A
IN1A
IN1A
+3.3V
V
L
CONFIG
PWRDN
R57
10K
R59
10K
C58
100nF
TH_WAR
IN1B
V
DD
V
DD
V
SS
V
SS
C58
100nF
C53
100nF
C60
100nF
IN2A
V
CC
SIGN
V
CC
SIGN
IN2A
GND-Reg
GND-Clean
21
22
33
34
M17
35
8
9
36
31
20
19
M16
M15
REGULATORS
7
V
CC
2A
C32
1µF
OUT2A
OUT2A
6
GND2A
PWRDN
FAULT
23
24
25
27
26
TRI-STATE
PROTECTIONS
&
LOGIC
M5
28
30
M4
13
M2
29
M3
15
17
16
C30
1µF
OUT1A
OUT1A
14
GND1A
C52
330pF
+V
CC
C55
1000µF
L18 22µH
C20
100nF
R98
6
C99
100nF
C23
470nF
C101
100nF
8Ω
12
V
CC
1B
C31
1µF
OUT1B
OUT1B
GND1B
R63
20
R100
6
C21
100nF
L19 22µH
11
10
TH_WAR
IN1B
L113 22µH
C110
100nF
C109
330pF R103
6
R104
20
C107
100nF
C108
470nF
C106
100nF
8Ω
4
V
CC
2B
C33
1µF
OUT2B
OUT2B
R102
6
C111
100nF
3
2
IN2B
IN2B
GNDSUB
32
M14
L112 22µH
1
5
GND2B
D00AU1148B
February 2006
Rev. 11
1/10
STA505
Table 2. Pin Function
N°
1
2;3
4
5
6
7
8;9
10 ; 11
12
13
14
15
16 ; 17
18
19
20
21 ; 22
23
24
29
25
26
27
28
29
30
31
32
33 ; 34
35 ; 36
Pin
GND-SUB
OUT2B
Vcc2B
GND2B
GND2A
Vcc2A
OUT2A
OUT1B
Vcc1B
GND1B
GND1A
Vcc1A
OUT1A
NC
GND-clean
GND-Reg
Vdd
VL
CONFIG
IN1A
PWRDN
TRI-STATE
FAULT
TH-WAR
IN1A
IN1B
IN2A
IN2B
Vss
Vcc Sign
Substrate ground
Output half bridge 2B
Positive Supply
Negative Supply
Negative Supply
Positive Supply
Output half bridge 2A
Output half bridge 1B
Positive Supply
Negative Supply
Negative Supply
Positive Supply
Output half bridge 1A
Not connected
Logical ground
Ground for regulator Vdd
5V Regulator referred to ground
High logical state setting voltage
Configuration pin
Input of half bridge 1A
Stand-by pin
Hi-Z pin
Fault pin advisor
Thermal warning advisor
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5V Regulator referred to +Vcc
Signal Positive Supply
Description
2/10
STA505
Table 3. Functional Pin Status
PIN NAME
FAULT
FAULT
(*)
TRI-STATE
TRI-STATE
PWRDN
PWRDN
THWAR
THWAR
(*)
CONFIG
CONFIG
(**)
Logical value
0
1
0
1
0
1
0
1
0
1
IC -STATUS
Fault detected (Short circuit, or Thermal ..)
Normal Operation
All powers in Hi-Z state
Normal operation
Low absorpion
Normal operation
Temperature of the IC =130C
Normal operation
Normal Operation
OUT1A=OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 3. Pin Connection
V
CC
Sign
V
CC
Sign
V
SS
V
SS
IN2B
IN2A
IN1B
IN1A
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
VL
VDD
VDD
GND-Reg
GND-Clean
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
D01AU1273
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND-SUB
OUT2B
OUT2B
V
CC
2B
GND2B
GND2A
V
CC
2A
OUT2A
OUT2A
OUT1B
OUT1B
V
CC
1B
GND1B
GND1A
V
CC
1A
OUT1A
OUT1A
N.C.
3/10
STA505
Table 4. Absolute Maximum Ratings
Symbol
V
CC
V
max
T
op
T
stg
, T
j
Parameter
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins 23 to 32
Operating Temperature Range
Storage and Junction Temperature
Value
40
5.5
-40 to 90
-40 to 150
Unit
V
V
°C
°C
Table 5. Thermal Data
Symbol
T
j-case
T
jSD
T
warn
t
hSD
Parameter
Thermal Resistance Junction to Case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
Thermal shut-down hysteresis
150
130
25
Min.
Typ.
Max.
2.5
Unit
°C/W
°C
°C
°C
Table 6. Electrical Characteristcs (V
L
= 3.3V; V
cc
= 30V; T
amb
= 25°C; f
sw
= 384Khz; unless otherwise
specified)
Symbol
R
dsON
I
dss
g
N
g
P
Dt_s
Dt_d
t
d ON
t
d OFF
t
r
t
f
V
CC
V
IN-High
V
IN-Low
I
IN-H
I
IN-L
Parameter
Power Pchannel/Nchannel
MOSFET RdsON
Power Pchannel/Nchannel
leakage Idss
Id=1A;
Vcc=35V
95
95
10
20
50
100
100
25
25
10
36
V
L
/2
+300mV
V
L
/2 -
300mV
Pin voltage = V
L
Pin voltage = 0.3V
1
1
Test conditions
Min.
Typ.
200
Max.
270
50
Unit
mΩ
µA
%
%
ns
ns
ns
ns
ns
ns
V
V
V
µA
µA
Power Pchannel RdsON Matching Id=1A
Power Nchannel RdsON
Matching
Low current Dead Time (static)
Id=1A
see test circuit no.1; see fig. 1
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8
Ω
Id=3.5A; see fig. 3
Turn-on delay time
Turn-off delay time
Rise time
Fall time
Supply voltage operating voltage
High level input voltage
Low level input voltage
High level Input current
Low level input current
Resistive load
Resistive load
Resistive load; as fig.1;
Resistive load; as fig. 1;
4/10
STA505
Symbol
Parameter
Test conditions
Min.
Typ.
35
0.8
1.7
3
Max.
Unit
µA
V
V
mA
I
PWRDN-H
High level PWRDN pin input
current
V
Low
V
High
I
VCC-
PWRDN
I
FAULT
Low logical state voltage VLow
V
L
= 3.3V
(pin PWRDN, TRISTATE) (note 1)
High logical state voltage VHigh
V
L
= 3.3V
(pin PWRDN, TRISTATE) (note 1)
Supply current from Vcc in Power
Down
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
Supply current from Vcc in Tri-
state
Supply current from Vcc in
operation
both channel switching)
Isc (short circuit current limit)
(note 2)
Undervoltage protection threshold
Output minimum pulse width
No Load
70
PWRDN = 0
Vpin = 3.3V
Tri-state=0
Input pulse width = 50% Duty;
Switching Frequency = 384KHz;
No LC filters;
3.5
1
22
50
mA
mA
mA
I
VCC-hiz
I
VCC
I
VCC-q
V
UV
t
pw-min
6
7
8
A
V
150
ns
Table 7.
Notes: 1. The following table explains the VLow, VHigh variation with V
L
V
L
2.7
3.3
5
VLow min
0.7
0.8
0.85
VHigh max
1.5
1.7
1.85
Unit
V
V
V
Note 2: See relevant Application Note AN1994
Table 8. Logic Truth Table (see fig. 5)
TRI-STATE
0
1
1
1
1
INxA
x
0
0
1
1
INxB
x
0
1
0
1
Q1
OFF
OFF
OFF
ON
ON
Q2
OFF
OFF
ON
OFF
ON
Q3
OFF
ON
ON
OFF
OFF
Q4
OFF
ON
OFF
ON
OFF
OUTPUT
MODE
Hi-Z
DUMP
NEGATIVE
POSITIVE
Not used
5/10
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