Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX;
SA56616-XX
GENERAL DESCRIPTION
The SA56616-XX and SA56615-XX CMOS system resets have low
consumption current of typically 1.0
µA
and high precision detection
voltage within
±2%.
The delay time is adjusted by an external
capacitor working in conjunction with the on-chip delay network. The
SA56615-XX and SA56616-XX have different output configurations
to accommodate a wide variety of microprocessors and logic
devices. The SA56615-XX incorporates a low side open-drain
output topology which requires a pull-up resistor to V
DD
, while the
SA56616-XX incorporates an active push-pull totem pole output
topology comprised of complimentary P-channel and N-channel
FETs.
The resets operate over a wide operating supply voltage range from
0.7 V to 10 V. Reset detection voltages are available at 0.9 V, 1.8 V,
1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V,
4.5 V, 4.6 V and 4.7 V. Other thresholds are offered upon request at
100 mV increments from 0.9 V to 6.0 V. The device comes in the
small outline 5-lead package (SOP003).
FEATURES
•
Super low supply current: typically 1.0
µA
(V
DD
= V
S
+ 1 V)
•
Operating supply voltage range: 0.7 V to 10 V
•
High precision detection voltage:
±2%
•
Detection voltage: 0.9 V, 1.8 V, 1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V,
3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, 4.6 V, and 4.7 V
APPLICATIONS
•
Microprocessor and logic circuit reset
•
Battery voltage level detection
•
Battery backup and switching circuits
•
Adjustable time delay circuits
•
Other detection threshold voltages available at 100 mV steps from
0.9 V to 6.0 V
•
User adjustable reset delay time
•
Versatile output configurations:
–
SA56615-XX: open-drain
–
SA56616-XX: N-channel/P-channel push-pull
SIMPLIFIED SYSTEM DIAGRAMS
V
DD
V
DD
2
V
IN
C
D
OUT
R
PU
RESET
LOGIC
SYSTEM
V
IN
C
D
V
DD
2
OUT
RESET
LOGIC
SYSTEM
V
DD
5
SA56615-XX
1
5
SA56616-XX
1
3
GND
GND
3
SL01596
SL01597
Figure 1. SA56615-XX simplified system diagram.
Figure 2. SA56616-XX simplified system diagram.
2003 Oct 15
2
Philips Semiconductors
Product data
CMOS system reset with adjustable delay time
SA56615-XX;
SA56616-XX
TYPICAL PERFORMANCE CURVES
NOTE:
Typical characteristics for SA56616-09
1.0
0.9
0.8
OUTPUT VOLTAGE (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.70
0
0.75
0.80
0.85
0.90
0.95
1.00
0
2
4
6
8
10
CONSUMPTION CURRENT (
µ
A)
INPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
TEMPERATURE (°C)
SL01743
SL01744
Figure 4. Output voltage versus input voltage.
Figure 5. Consumption current versus input voltage.
0.40
V
DS
= 0.5 V
C
D
PIN OUTPUT CURRENT (mA)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
DELAY TIME (ms)
1000
100
10
1
0
0.2
0.4
0.6
0.8
1.0
0.1
0.0001
0.001
0.01
C
D
(µF)
0.1
1
INPUT VOLTAGE (V)
SL01745
SL01746
Figure 6. C
D
pin output current versus input voltage.
Figure 7. Delay time versus C
D
.
1.00
80
70
HYSTERESIS VOLTAGE (mV)
DETECTING VOLTAGE (V)
0.95
60
50
40
30
20
10
0.90
0.85
0.80
–40
–20
0
20
40
60
80
100
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
SL01747
SL01748
Figure 8. Detection voltage versus temperature.
Figure 9. Hysteresis voltage versus temperature.
2003 Oct 15
5
FPGA/CPLD
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