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SN74ABT7819
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
D
D
D
D
D
D
Member of the Texas Instruments
Widebus™ Family
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Read and Write Operations Synchronized
to Independent System Clocks
Two Separate 512
×
18 Clocked FIFOs
Buffering Data in Opposite Directions
IRA and ORA Synchronized to CLKA
IRB and ORB Synchronized to CLKB
D
D
D
D
D
D
Microprocessor Interface Control Logic
Programmable Almost-Full/Almost-Empty
Flag
Fast Access Times of 9 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
Data Rates up to 100 MHz
Advanced BiCMOS Technology
Package Options Include 80-Pin Quad Flat
(PH) and 80-Pin Thin Quad Flat (PN)
Packages
PH PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
CSA
W/RA
GND
WENA
CLKA
RENA
ORA
V
CC
V
CC
ORB
RENB
CLKB
WENB
GND
W/RB
CSB
RSTA
PENA
AF/AEA
HFA
IRA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
A11
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RSTB
PENB
AF/AEB
HFB
IRB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
B11
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
A12
A13
V
CC
A14
A15
GND
A16
A17
B17
B16
GND
B15
B14
V
CC
B13
B12
Copyright
©
1998, Texas Instruments Incorporated
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1
SN74ABT7819
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
PN PACKAGE
(TOP VIEW)
PENA
RSTA
CSA
W/RA
GND
WENA
CLKA
RENA
ORA
V
CC
V
CC
ORB
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RENB
CLKB
WENB
GND
W/RB
CSB
RSTB
PENB
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AF/AEA
HFA
IRA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AF/AEB
HFB
IRB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two
independent 512
×
18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags
to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN74ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0–A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs
are active. The A0–A17 outputs are in the high-impedance state when either CSA or W/RA is high. Data is
written to FIFOA–B from port A on the low-to-high transition of CLKA when CSA is low, W/RA is high, WENA
is high, and the IRA flag is high. Data is read from FIFOB–A to the A0–A17 outputs on the low-to-high transition
of CLKA when CSA is low, W/RA is low, RENA is high, and the ORA flag is high.
2
A11
GND
A12
A13
V
CC
A14
A15
GND
A16
A17
B17
B16
GND
B15
B14
V
CC
B13
B12
GND
B11
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•
DALLAS, TEXAS 75265
SN74ABT7819
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
description (continued)
The state of the B0–B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs
are active. The B0–B17 outputs are in the high-impedance state when either CSB or W/RB is high. Data is
written to FIFOB–A from port B on the low-to-high transition of CLKB when CSB is low, W/RB is high, WENB
is high, and the IRB flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the low-to-high transition
of CLKB when CSB is low, W/RB is low, RENB is high, and the ORB flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable write and read operations on memory and are not related to the high-impedance control of the data
outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock
cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the
data outputs.
The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for
use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the
output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB)
and the output-ready flag of FIFOA–B (ORB). When the IR flag of a port is low, the FIFO receiving input from
the port is full and writes are disabled to its array. When the OR flag of a port is low, the FIFO that outputs data
to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent
to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and
the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high)
again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.
The SN74ABT7819 is characterized for operation from 0°C to 70°C.
Function Tables
PORT A
SELECT INPUTS
CLKA
X
↑
↑
CSA
H
L
L
W/RA
X
H
L
WENA
X
H
X
RENA
X
X
H
PORT B
SELECT INPUTS
CLKB
X
↑
↑
CSB
H
L
L
W/RB
X
H
L
WENB
X
H
X
RENB
X
X
H
B0–B17
B0 B17
High Z
High Z
Active
PORT-B
PORT B OPERATION
None
Write B0–B17 to FIFOB–A
Read FIFOA–B to B0–B17
A0–A17
A0 A17
High Z
High Z
Active
PORT-A
PORT A OPERATION
None
Write A0–A17 to FIFOA–B
Read FIFOB–A to A0–A17
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•
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3
SN74ABT7819
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
logic symbol
†
CLKA
CSA
W/RA
76
80
79
CLOCK A
&
OE1
Φ
FIFO 512
×
18
×
2
SN74ABT7819
CLOCK B
&
OE2
69
65
66
CSB
W/RB
&
77
&
75
1
RSTA
PENA
IRA
ORA
HFA
AF/AEA
2
5
74
4
3
&
68
&
70
64
63
60
71
61
62
CLKB
WENA
WRITE
ENABLE
FIFOA–B
READ
ENABLE
FIFOB–A
WRITE
ENABLE
FIFOB–A
WENB
RENA
READ
ENABLE
FIFOA–B
RENB
RSTB
PENB
IRB
ORB
HFB
AF/AEB
RESET FIFO A–B
PROGRAM ENABLE
FIFO A–B
INPUT-READY
PORT A
OUTPUT-READY
PORT A
HALF-FULL
FIFOA–B
ALMOST-FULL/EMPTY
FIFOA–B
0
RESET FIFO B–A
PROGRAM ENABLE
FIFO B–A
INPUT-READY
PORT B
OUTPUT-READY
PORT B
HALF-FULL
FIFOB–A
ALMOST-FULL/EMPTY
FIFOB–A
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
7
8
10
11
13
14
16
17
19
20
22
23
25
26
28
29
31
32
58
57
55
54
52
51
49
48
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
1
Data
Data
2
46
45
43
42
40
39
37
36
34
17
17
33
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the PH package.
4
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•
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