OMC 952723134
Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073A
Preface
The H8/3048 Series is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been
expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to
reduce power consumption in battery-powered applications: individual modules can be placed in
standby, and the frequency of the system clock supplied to the chip can be divided down under
software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3048 Series can be used to implement compact, high-performance
systems easily.
In addition to its masked-ROM versions, the H8/3048 Series has a ZTAT™*
1
version with user-
programmable on-chip PROM and an F-ZTAT™*
2
version with on-chip flash memory that can be
programmed on-board. These versions enable users to respond quickly and flexibly to changing
application specifications.
This manual describes the H8/3048 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Notes: 1. ZTAT™ (Zero Turn-Around-time) is a trademark of Hitachi, Ltd.
2. F-ZTAT™ (Flexible ZTAT) is a trademark of Hitachi, Ltd.
Main Revisions and Additions in this Edition
Page Item
1
2
7
61
1.1
Table 1-1
Table 1-2
3.6
Overview
Features
Pin Assignments in Each
Mode (FP-100B or TFP-100B)
Memory Map in Each Operating Mode
H8/3044 Memory Map in Each Operating Mode
H8/3045 Memory Map in Each Operating Mode
External-Bus-Released State
(Two-State-Access Area, During Read Cycle)
Refresh Control Register (RFSHCR)
Usage Notes
Operation when DRAM/PSRAM
Connection is Switched
Features
DMAC Functional Overview
Memory Address Registers (MAR)
I/O Address Registers (IOAR)
DMAC Modes
I/O Mode
Register Functions in I/O Mode
Idle Mode
Register Functions in Idle Mode
Repeat Mode
Port 6 Resisters
Pin Functions in Each Mode
Pin Functions
Example of SCI Receive Operation
(8-Bit Data with Parity and One Stop Bit)
Revisions
H8/3045 added
H8/3045 added
Table amended
H8/3045 added
Address amended
Figure added
Figure amended
Bit 5 amended
Description and note
added
Figure amended
Description added
Table amended
Description added
Description added
Table amended
Description added
Description added
Description added
Description added
Description amended
Mode6,7 added
Section added
Section added
66, 67 Figure 3-3
68, 69 Figure 3-4
141
149
181
Figure 6-19
7.2.1
7.5
Figure 7-23
183
185
188
189
203
205
207
208
210
260
8.1.1
Table 8-1
8.2.1
8.2.2
Table 8-5
8.4.2
Table 8-6
8.4.3
Table 8-7
8.4.4
Table 9-10
277 to 9.11.3
281
286 to 9.12.3
291
473
Figure 13-8
Figure amended
Page Item
479
Figure 13-13
Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One
Stop Bit)
Overview
Operation
Overview
Socket Adapter Pin Assignments
Flash Memory Control Register
Automatic Alignment of SCI Bit Rate
System Clock Frequencies Permitting Automatic
Bit-Rate Alignment by H8/3048F
RAM Area Allocation in Boot Mode
RAM Areas in Boot Mode
Notes on Use of Boot Mode
Figure 18-13
18.7
Figure 18-14
18.7.1
18.7.3
Figure 18-15
User Program Mode Operation (Example)
Programming and Erasing Flash Memory
Flash Memory Program/Erase Operating Mode
State Transition Diagram
Program Mode
Programming Flowchart and Sample Program
Programming Flowchart
Sample Program for Programming One Byte
18.7.4
18.7.5
18.7.6
Figure 18-16
Figure 18-17
Erase Mode
Erase-Verify Mode
Erasing Flowchart and Sample Program
Erasing Flowchart
Prewrite Flowchart
Sample Program for Erasing One Block
Multiple-Block Erase Flowchart
Sample Program for Erasing Multiple Blocks
Revisions
Figure amended
547
550
551
554
568
579
17.1
17.3
18.1
Figure 18-2
18.5.1
H8/3045 added
H8/3045 added
H8/3045 added
Note added
Description and note
added
Description amended
Note added
Address amended
Figure amended
and note added
(6),(7) added
Figure amended
Description added
Figure added
Description amended
Description amended
Figure and note
amended
Program amended
Description amended
Description amended
Description amended
Figure and note
amended
Figure and note
amended
Program amended
Figure and note
amended
Program amended
Table 18-13
580
Figure 18-12
581
582
583
584
585
586,
587
587
588
589
590
591 to 593
594
Figure 18-18
595 to 599
Page Item
600
601
602
606
609
613
614
615
618
619
620
623
624
Figure 18-32
Table 18-14
18.7.7
18.7.8
Figure 18-20
Figure 18-22
Figure 18-24
Table 18-22
Table 18-23
18.10
Figure 18-28
Figure 18-29
Loop Counter Values in Program (10 MHz)
Prewrite-Verify Mode
Hardware Protection
Example of RAM Overlap
Wiring of Socket Adapter
High-Speed, High-Reliability Erasing
DC Characteristics in PROM Mode
AC Characteristics in PROM Mode
Flash Memory Programming and
Erasing Precautions
Power-On and Power -Off Timing (Boot Mode)
Power-On and Power-Off Timing
(User Program Mode)
Revisions
Formula amended
Description and note
amended
Note added
Note deleted
Figure amended and
note added
Note amended
Table amended
Table amended
Description amended
Figure added and
amended
Figure added and
amended
(8) Notes concerning mounting board development
-handling of Vpp and mode MD2 pins
Description amended
Example of Mounting Board Design
(Connection to Adapter Board- When Vpp Pin
and Mode Pin Setting Are 1)
Notes on Ordering Masked ROM Version Chip
Damping Resistance Value
External Clock
Clock Timing
External Clock Output Setting Delay Timing
Absolute Maximum Ratings
DC Characteristics
Figure added
Section added
Note amended
Description amended
Item added
Figure added
Item and note added
Item “Output high
voltage” description
amended
Item added
Table amended
Table amended
Item added
625
628
631
18.11
Table 19-1
Table 19-3
632
649
650,
653
663
668
672
680
Figure 19-7
Table 21-1
Table 21-2
Table 21-6
Table 21-10
Table 21-10
Table 21-14
Control Signal Timing
DC Characteristics
DC Characteristics (cont)
Control Signal Timing
FPGA/CPLD
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