NM27C520 524,288-Bit (64K x 8) Multiplexed Addresses/Outputs
OTP CMOS EPROM
Connection Diagram
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7
DS800001-2
Pin Names
Addresses/Outputs
AD
0
-AD
7
A
8
-A
15
ALE
OE/V
PP
Address/Data
Address
Address Latch Enable
Output Enable
SOIC Top View
Commercial Temp. Range
(0°C to + 70°C)
V
CC
= 5V
±
10%
Parameter/Order Number
NM27C520M 90
Access Time (ns)
(Note 1)
90
Industrial Temp. Range
(-40°C to + 85°C)
V
CC
= 5V
±
10%
Parameter/Order Number
NM27C520ME 90
Note 1:
All versions are guaranteed to function for slower speeds.
Access Time (ns)
(Note 1)
90
Package Type:
M=Wide Bodied SOIC
2
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NM27C520 524,288-Bit (64K x 8) Multiplexed Addresses/Outputs
OTP CMOS EPROM
Absolute Maximum Ratings
(Note 2)
Storage Temperature
All Input Voltage except A9
with Respect to Ground
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
(MIL Std. 883, Method 3015.2)
All Output Voltages with
Respect to Ground
-65°C to +150°C
-2.0V to +7V
-2.0V to +14V
-0.6V to +7V
>2000V
V
CC
+1.0V to GND -0.6V
Operating Range
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
+5V
+5V
Tolerance
±10%
±10%
Read Operation
DC Electrical Characteristics
Symbol
V
IL
V
IH
V
OL
V
OH
I
CC
I
CC2
I
PP
V
PP
I
LI
I
LI2
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Active Current
V
CC
Standby Current
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Input Load Current A13
Output Leakage Current
Test Conditions
Min.
-0.6
2.0
Max.
0.8
V
CC
+ 0.5
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -400µA
I
OUT
= 0 mA, f = 5 MHz
ALE = V
IH
V
PP
= V
CC
V
CC
- 0.7
V
IN
= 5.5V or GND
V
IN
= 5.5V or GND
V
OUT
= 5.5V or GND
-1
-100
-5
2.4
20
2
10
V
CC
1
100
5
mA
mA
µA
V
µA
µA
µA
Read Operation
AC Electrical Characteristics
Symbol
t
ACC
t
ALE
t
OE
t
DF
t
OH
t
AS
t
AH
Parameter
Address to Output Delay
Address Latch Enable Width
OE to Output Delay
Output Disable to Output Float
Output Hold from Addresses, CE
or OE, whichever Occurred First
Address Setup Time
Address Hold Time
Min
45
Max
90
Units
ns
ns
35
25
0
15
15
ns
ns
ns
ns
ns
3
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NM27C520 524,288-Bit (64K x 8) Multiplexed Addresses/Outputs
OTP CMOS EPROM
Capacitance
T
A
= +25°C, f = 1 MHz (Note 3)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
4
8
Max
6
12
Units
pF
pF
AC Test Conditions
Output Load
1 TTL Gate and CL = 100 pF (Note 9)
≤
20 ns (10% to 90%)
0.45V to 2.4V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level (Note 9)
Inputs
0.8V and 2.0V
Outputs
0.8V and 2.0V
AC Waveforms for Read Operation
(Notes 7 and 8)
tALE
ALE
OE/VPP
t
AS
AD0 - AD7
t
AH
t
OE
(Note 4)
ADDRESS IN
DATA OUT
t
DF
(Note 5, 6)
t
OH
t
ACC
(Note 4)
A8 - A15
DS800001-3
Note 2:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 3:
This parameter is only sampled and is not 100% tested.
Note 4:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of ALE without impacting t
ACC
.
High to TRI-STATE, the measured V
OH1
(DC) -0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) +0.10V.
Note 6:
TRI-STATE may be attained using OE or CE.
Note 7:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 8:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 9:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 5:
The t
DF
and t
CF
compare level is determined as follows:
4
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NM27C520 524,288-Bit (64K x 8) Multiplexed Addresses/Outputs
OTP CMOS EPROM
DC Programming Characteristics
(Notes 11 & 12)
T
A
= 25
±
5°C, V
CC
= 6.5
±
2.5V, OE/V
PP
= 13.0
±
0.25V (Note 13)
Symbol
V
IL
V
IH
V
OL
V
OH
I
CC
I
CC2
I
PP
I
LI
I
LI2
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Supply Current
V
CC
Standby Current
OE/V
PP
Current
Input Load Current
Input Load Current A13
Test Conditions
Min
-0.6
2.0
Typ
Max
0.8
V
CC
+ 1
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -400
µA
2.4
25
ALE = V
IL
ALE = V
IH
V
IN
= V
IL
or V
IH
V
IN
= V
IL
or V
IH
-10
-100
2.5
25
10
100
mA
mA
mA
µA
µA
AC Programming Characteristics
(Notes 11 & 12)
T
A
= 25
±
5°C, V
CC
= 6.5
±
2.5V, OE/V
PP
= 13.0
±
0.25V (Note 13)
Symbol
t
ALE
t
LAS
t
LAH
t
AS
t
AH
t
DS
t
DH
t
OES
t
OEH
t
PRT
t
VR
t
PW
t
VCS
t
LP
t
OE
t
DFP
Parameter
Address Latch Enable Width
Latched Address Setup Time
Latched Address Hold Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE/V
PP
Setup Time
OE/V
PP
Hold Time
OE/V
PP
Pulse Rise Time
during Programming
OE/V
PP
Recovery Time
Program Pulse Width
V
CC
Setup Time
ALE Low to OE/V
PP
High
Voltage Delay
Data Valid from OE/V
PP
OE/V
PP
High to Output Float
Delay (Note 14)
Test Conditions
Min
500
100
100
2
2
2
2
2
2
50
2
45
2
2
Typ
Max
Units
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
µs
50
105
µs
µs
µs
150
0
130
ns
ns
Note 11:
Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 13:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µF
capacitor is required across V
CC
to GND to suppress spurious voltage transients which
may damage the device.
Note 14:
This parameter is not 100% tested. Output Float is defined as the point where data is no longer driven. See timing diagram (page 6).
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