TOSHIBA
TLCS-90 Series
CMOS 8–Bit Microcontrollers
(2)
TMP90CH02/H03
TMP90CH02P/TMP90CH02M
(3)
TMP90CH03P/TMP90CH03M
1. Outline and Characteristics
The TMP90CH02 is a high-speed advanced 8-bit microcontroller
applicable to a variety of equipment.
With its 8-bit CPU, ROM, RAM, timer/event counter and
general-purpose serial interface integrated into a single CMOS
chip, the TMP90CH02 allows the expansion of external memo-
ries for programs (up to 48K byte). The TMP90CH03 is the
same as the TMP90CH02 bit without the ROM.
The TMP90CH02P/H03P is in a DIP ppackage.
The TMP90CH02M/H03M is in a SOP (Small Outline
Package).
The characteristics of the TMP90CH02 include:
(1)
Powerful instructions: 163 basic instructions, including
Multiplication, division, 16-bit arithmetic operations, bit
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
manipulation instructions
Minimum instruction executing time: 250ns
(at 16MHz oscillation frequency)
Internal ROM: 16K byte (the TMP90CH03 does not
have a built in ROM)
Internal RAM: 512 byte
Memory expansion
External memory: 48K byte
General-purpose serial interface (1 channel)
Asynchronous mode, I/O interface mode
8-bit timers (4 channels): (1 external clock input)
Port with zero cross detection circuit (1 input)
Input/Output ports (90CH02: 32 pins, 90CH03: 6 pins)
Interrupt function: 8 internal interrupts and 3 external
interrupts
Micro Direct Memory Access (DMA) function (4 channels)
Watchdog timer
Standby function (4 HALT modes)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
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TMP90CH02/H03
Figure 1. TMP90CH02 Block Diagram
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TOSHIBA CORPORATION
TMP90CH02/H03
2. Pin Assignment and Functions
The assignment of input/output pins, their names and functions
are described below.
2.1 Pin Assignment
Figure 2.1 (1) shows pin assignment of the TMP90CH02/
CH03.
Figure 2.1 (1). Pin Assignment (Shrink Dual Inline Package)
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TMP90CH02/H03
2.2 Pin Names and Functions
The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/1)
Pin Name
P00 ~ P07
/D0 ~ D7
No. of Pins
8
I/O 3 states
I/O
Function
Port 0: 8-bit I/O port that allows selection of input/output on byte basis
Data Bus: Also functions as 8-bit bidirectional data bus for external memory
(For CH03, fixed to databus)
Port 1: 8-bit I/O port that allows selection on byte basis
Addrress Bus: The lower 8 bits address bus for external memory
(For CH03, fixed to address bus)
Port 2: 8-bit I/O port that allows selection on byte basis
Addrress Bus: The uppper 8 bits address bus for external memory
(For CH03, fixed to address bus)
Port 31: 1-bit input port
Receives serial data
Port 32: 1-bit output port
3 states
I/O
P10 ~ P17
/A0 ~ A7
8
Output
I/O
P20 ~ P27
/A8 ~ A 15
P31
/RxD
P32
/TxD
/RTS
/SCLK
P33
/TxD
P35
/RD
P36
/WR
P37
/WAIT
8
Output
1
Input
1
Output
Serial clock output
1
Output
Port 33: 1-bit output port
Transmits serial data
Port 35: 1-bit output port
Read: Generates strobe signal for reading external memory
Port 36: 1-bit output port
Writes: Generates strobe signal for writing external memory
Port 37: 1-bit input port
Wait: Input pin for connecting slow speed memory or peripheral LSI
Port 80: 1-bit input port
1
Output
1
Output
1
Input
P80
/INTO
1
Input
Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)
Port 81: 1-bit input port
P81
/INT1
/TI4
Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable)
1
Input
Timer input 4: Counter/capture trigger signal for Timer 4
Non-maskable interrupt request pin: Falling edge interrupt request pin
NMI
CLK
EA
RESET
X1/X2
V
CC
V
SS
(GND)
1
1
1
1
2
1
1
Input
Output
Input
Input
Input/
Output
–
–
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is Pulled up
internally during resetting.
External access: Connects with GND pin in the TMP90C802A using internal ROM, and
with GND pin in the TMP90C803A with no internal ROM.
Reset: Initializes the TMP 90CH02/CH03. (Built-in pull-up resistor)
Pin for quartz crystal or ceramic resonator (1 ~ 16MHz)
Power supply (+5V)
Ground (0V)
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TOSHIBA CORPORATION
TMP90CH02/H03
3. Operation
The following explains the TMP90CH02 functions and basic
operations. The CPU functions and internal I/O functions of the
TMP90CH02 are the same as the TMP90C840A.
Refer to the “TMP90C840A” section concerning functions
which are not explained the following.
3.1 CPU
The TMP90CH02 has an internal high-performance 8-bit CPU.
Refer to the book TLCS Series CPU Core Architecture
concerning CPU operation.
3.2 Memory Map
The TMP90CH02 supports a program memory of up to 64K
bytes.
The program memory may be assigned to the address
space from 00000H to 0FFFFH, while the data memory can be
allocated to any address from 0000H to FFFFH.
(1)
Internal ROM
The TMP90CH02 internally contains a 16K byte ROM.
The address space from 0000H to 3FFFH is provided
to the ROM. The CPU starts executing a program from
0000H by resetting.
The addresses from 0010H to 007FH in this internal
ROM area are used for the entry area for the interrupt
processing.
The TMP90CH03 does not have a built-in ROM; there-
fore, the address space 0000H ~ 3 FFFH is used as
external memory space.
(2)
Internal RAM
The TMP90CH02 also contains a 512-byte RAM,
which is allocated to the address space FDC0H ~
FFBFH. The CPU allows the access to whole RAM
area (FF00H ~ FFBFH, 192 bytes) by a short operation
code (opcode) in the “direct addressing mode”.
The addresses from FF30H ~ FF7FH in this RAM area
can be used as parameter area for micro DMA pro-
cessing (and for any other purposes when the micro
DMA function is not used).
(3)
Internal I/O
The TMP90CH02 provides a 48-byte address space
as an internal I/O area, whose addressess range from
FFC0H to FFEFH. This I/O area can be accessed by
the CPU using a short opcode in the “direct addressing
mode”.
Figure 3.2 is a memory map indicating the areas acces-
sible by the CPU in the respective addressing mode.
TOSHIBA CORPORATION
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FPGA/CPLD
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