FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13737-6E
16-bit Microcontroller
CMOS
F
2
MC-16LX MB90350 Series
MB90F351(S), MB90F352(S),MB90F351A(S), MB90F351TA(S), MB90F352A(S), MB90F352TA(S),
MB90F356A(S), MB90F356TA(S), MB90F357A(S), MB90F357TA(S),MB90351A(S), MB90351TA(S),
MB90352A(S), MB90352TA(S),MB90356A(S), MB90356TA(S), MB90357A(S), MB90357TA(S),
MB90V340A-101/102/103/104
■
DESCRIPTION
The MB90350-series with 1 channel FULL-CAN interface and Flash ROM is especially designed for automotive
and industrial applications. Its main feature is the on-board CAN interface, which conforms to V2.0 Part A and
Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full
CAN approach. With the new 0.35
μm
CMOS technology, FUJITSU SEMICONDUCTOR now offers on-chip Flash-
ROM program memory up to 128 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external
4 MHz clock. Also, the clock monitor function can monitor main clock and sub clock independently.
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit,
2 separate 16-bit freerun timers, 2-channel UART and 15-channel 8/10-bit A/D converter.
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
For the information for microcontroller supports, see the following web site.
This web site includes the
"Customer Design Review Supplement"
which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2003-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.9
MB90350 Series
■
FEATURES
•
Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-
plied PLL clock).
• Built-in clock modulation circuit
•
16 Mbytes CPU memory space
• 24-bit internal addressing
•
Clock monitor function (MB90x356x and MB90x357x only)
• Main clock or sub clock is monitored independently.
• Internal CR oscillation clock (100 kHz typical) can be used as sub clock.
•
Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
•
Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
•
Increased processing speed
• 4-byte instruction queue
•
Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported.
•
Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI
2
OS) : up to 16 channels
• DMA : up to 16 channels
•
Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
•
Process
• CMOS technology
(Continued)
2
DS07-13737-6E
MB90350 Series
•
I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix : devices that correspond to sub clock)
- 51 ports (devices with S-suffix : devices that do not correspond to sub clock)
•
Sub clock pin (X0A, X1A)
• Yes (using the external oscillation) : devices without S-suffix
• No (using the sub clock mode at internal CR oscillation) : devices with S-suffix
•
Timer
• Timebase timer, watch timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit
×
10 channels or 16-bit
×
6 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit freerun timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
•
FULL-CAN interface : 1 channel
• Compliant with Ver2.0 part A and Ver2.0 part B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
•
UART (LIN/SCI) : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available.
•
I
2
C interface : 1 channel
• Up to 400 Kbit/s transfer rate
•
DTP/External interrupt : 8 channels, CAN wakeup : 1 channel
• Module for activation of extended intelligent I/O service (EI
2
OS), DMA, and generation of external interrupt by
external input.
•
Delay interrupt generator module
• Generates interrupt request for task switching.
•
8/10-bit A/D converter : 15 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3
μs
(at 24-MHz machine clock, including sampling time)
•
Program patch function
• Address matching detection for 6 address pointers.
•
Capable of changing input voltage level for port
• Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)
• TTL level (corresponds to external bus pins only, initial level of these pins is TTL in external bus mode)
•
Low voltage/CPU operation detection reset (devices with T-suffix)
• Detects low voltage (4.0 V
±
0.3 V) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(approx. 262 ms : external 4 MHz)
(Continued)
DS07-13737-6E
3
MB90350 Series
(Continued)
•
Dual operation flash memory (only flash memory devices with A-suffix)
• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
•
Models that support
+
125
°C
• Devices without A-suffix (excluding evaluation device) : The maximum operating frequency is 16 MHz
(at T
A
= +125 °C)
.
• Devices with A-suffix (excluding evaluation device)
: The maximum operating frequency is 24 MHz
(at T
A
= +125 °C)
.
•
Flash security function
• Protects the content of Flash memory (MB90F352x and MB90F357x only)
•
External bus interface
• 4 Mbytes external memory space
4
DS07-13737-6E
MB90350 Series
■
PRODUCT LINEUP 1
Part Number
Parameter
CPU
System clock
ROM
RAM
Emulator-specific
power supply*
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Clock monitor
function
Low voltage/CPU
operation detection
reset
Operating
voltage range
Operating
temperature range
Package
No
No
Yes
No
MB90F351,
MB90F352
MB90F351S,
MB90F352S
MB90F351A,
MB90F352A
MB90F351TA, MB90F351AS,
MB90F351TAS,
MB90F352TA MB90F352AS
MB90F352TAS
F
2
MC-16LX CPU
On-chip PLL clock multiplier (×1,
×2, ×3, ×4, ×6,
1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL
×
6)
Flash memory
64Kbytes : MB90F351(S)
128Kbytes : MB90F352(S)
Dual operation flash memory
64Kbytes : MB90F351A(S), MB90F351TA(S)
128Kbytes : MB90F352A(S), MB90F352TA(S)
4 Kbytes
⎯
Yes
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
−40 °C
to
+105 °C
(+125
°C
up to 16 MHz machine clock)
LQFP-64
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3
μs
includes sample time (per one channel)
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
=
Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
−40 °C
to
+125 °C
UART
I
2
C (400 Kbps)
A/D Converter
16-bit Reload Timer
(4 channels)
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
=
Machine clock frequency)
4 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
16-bit Output
Compare
DS07-13737-6E
5
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