CM1236
PicoGuard XS
TM
ESD Clamp Array For High Speed Data Line Protection
Features
•
•
ESD protection for 4 pairs of differential channels
ESD protection to:
• IEC61000-4-2 Level 4 (ESD) at ±8kV contact
discharge
• IEC61000-4-4 (EFT) 40A (5/50ns)
• IEC61000-4-5 (Lighting) 3.5A (8/20μs)
Pass-through impedance matched clamp
architecture
Flow-through routing for high-speed signal integrity
Minimal line capacitance change with temperature
and voltage
100Ω matched impedance for each paired
differential channel
Each I/O pin can withstand over 1000 ESD strikes*
RoHS compliant (lead-free) TDFN-16 package
Product Description
The
PicoGuard XS
(Xtreme
Speed)
protection family is
specifically designed for next generation deep sub-
micron high speed data line protection.
The CM1236 is ideal for protecting systems with high
data and clock rates or for circuits requiring low
capacitive loading and tightly controlled signal skews
(with channel-to-channel matching at 2% max
deviation).
The device is particularly well-suited for protecting
systems using high-speed ports such as DisplayPort or
HDMI, along with corresponding ports in removable
storage, digital camcorders, DVD-RW drives and other
applications where extremely low loading capacitance
with ESD protection are required.
The CM1236 also features easily routed "pass-
through" pinouts in a RoHS compliant (lead-free),16-
lead TDFN, small footprint package.
•
•
•
•
•
•
Applications
•
•
DVI , DisplayPort, and HDMI ports in notebooks, set
top boxes, digital TVs, and LCD displays
General purpose high-speed data line ESD
protection
Electrical Schematic
Out_1+
Out_1-
Out_2+
Out_2-
Out_3+
Out_3-
Out_4+
Out_4-
In_1+
In_1-
In_2+
In_2-
In_3+
In_3-
In_4+
In_4-
Gnd
= 100Ω differential
matched characteristic
impedance
*
Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to ±8kv contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test
run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes.
© 2009 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 02/24/09
●
Fax: 408.263.7846
●
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1
CM1236
PicoGuard XS
ESD Protection Archi-
tecture
Conceptually, an ESD protection device performs the
following actions upon an ESD strike discharge into a
protected ASIC (see
Figure 1):
1. When an ESD potential is applied to the system
under test (contact or air-discharge), Kirchoff’s
Current Law (KCL) dictates that the Electrical
Overstress (EOS) currents will immediately divide
throughout the circuit, based on the dynamic
impedance of each path.
2. Ideally, the classic shunt ESD clamp will switch
within 1ns to a low-impedance path and return the
majority of the EOS current to the chassis shield/
reference ground. In actuality, if the ESD compo-
nent's response time (t
CLAMP
) is slower than the
ASIC it is protecting, or if the Dynamic Clamping
Resistance (R
DYN
) is not significantly lower than
the ASIC's I/O cell circuitry, then the ASIC will have
to absorb a large amount of the EOS energy, and
be more likely to fail.
3. Subsequent to the ESD/EOS event, both devices
must immediately return to their original specifica-
tions, and be ready for an additional strike. Any
deterioration in parasitics or clamping capability
should be considered a failure, since it can then
affect signal integrity or subsequent protection
capability. (This is known as "multi-strike" capabil-
ity.)
In the CM1236
PicoGuard XS
architecture, the signal
line leading the connector to the ASIC routes through
the CM1236 chip which provides 100Ω matched
differential channel characteristic impedance that helps
optimize 100Ω load impedance applications such as
the HDMI high speed data lines.
Note:When each of the channels are used individually
for single-ended signal lines protection, the indi-
vidual channel provides 50Ω characteristic imped-
ance matching.
The load impedance matching feature of the CM1236
helps to simplify system designer’s PCB layout
considerations in impedance matching and also
eliminates associated passive components.
The route through the
PicoGuard XS
architecture
enables the CM1236 to provide matched impedance
for the signal path between the connector and the
ASIC. Besides this function, this circuit arrangement
also changes the way the parasitic inductance interacts
with the ESD protection circuit and helps reduce the
I
RESIDUAL
current to the ASIC.
ESD Strike
ESD
ESD
Protection
PROTECTION
Device
DEVICE
I /O
Connector
ASIC
I
SHUNT
I
RESIDUAL
Figure 1. Standard ESD Protection Device Block Diagram
© 2009 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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CM1236
The
PicoGuard XS
Architecture Advantages
Figure 2
illustrates a standard ESD protection device.
The inductor element represents the parasitic
inductance arising from the bond wire and the PCB
trace leading to the ESD protection diodes.
element. This limits the speed that the ESD pulse can
discharge through the ESD protection element.
In the
PicoGuard XS
architecture, the inductive
elements are in series to the conduction path leading
to the protected device. The elements actually help to
limit the current and voltage striking the protected
device.
First the reactance of the inductive element, L1, on the
connector side when an ESD strike occurs, acts in the
opposite direction of the ESD striking current. This
helps limit the peak striking voltage. Then the
reactance of the inductive element, L2, on the ASIC
side forces this limited ESD strike current to be
shunted through the ESD protection diodes. At the
same time, the voltage drop across both series
element acts to lower the clamping voltage at the
protected device terminal.
Through this arrangement, the inductive elements also
tune the impedance of the ESD protection element by
cancelling the capacitive load presented by the ESD
diodes to the signal line. This improves the signal
integrity and makes the overall ESD protection device
more transparent to the high bandwidth data signals
passing through the channel.
The innovative
PicoGuard XS
architecture turns the
disadvantages of the parasitic inductive elements into
useful components that help to limit the ESD current
strike to the protected device and also improves the
signal integrity of the system by balancing the
capacitive loading effects of the ESD diodes. At the
same time, this architecture provides an impedance
matched signal path for 50Ω loading applications.
Board designs can take advantage of precision internal
component matching for improved signal integrity,
which is not otherwise possible with discrete
components at the system level. This helps to simplify
the PCB layout considerations by the system designer
and eliminates the associated passive components for
load matching that is normally required with standard
ESD protection circuits.
Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current
pulse to either the Zener diode or to ground. This
embedded Zener diode also serves to eliminate the
need for a separate bypass capacitor to absorb
positive ESD strikes to ground. The CM1236 protects
against ESD pulses up to ±8kv contact per the IEC
61000-4-2 standard.
Connector
ASIC
Bond Wire
Inductance
ESD
Stage
Figure 2. Standard ESD Protection Model
Figure 3
illustrates one of the channels. Similarly, the
inductor elements represent the parasitic inductance
arising from the bond wire and PCB traces leading to
the ESD protection diodes as well.
Connector
50Ω
L1
L2
ASIC
ESD
Device
Figure 3. CM1236
PicoGuard XS
ESD Protection
Model
CM1236 Inductor Elements
In the CM1236
PicoGuard XS
architecture, the
inductor elements and ESD protection diodes interact
differently compared to the standard ESD model.
In the standard ESD protection device model, the
inductive element presents high impedance against
high slew rate strike voltage, i.e. during an ESD strike.
The impedance increases the resistance of the
conduction path leading to the ESD protection
© 2009 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 02/24/09
●
Fax: 408.263.7846
●
www.cmd.com
3
CM1236
Package/Pin Information
PACKAGE / PINOUT DIAGRAMS
Bottom View (Solder Side)
Out_1+
Out_1-
Out_2+
Out_2-
Out_3+
Out_3-
Out_4+
Out_4-
In_1+
In_1-
In_2+
In_2-
In_3+
In_3-
In_4+
In_4-
Note:
1) This drawing is not to scale.
PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PAD
Name
In_1+
In_1-
In_2+
In_2-
In_3+
In_3-
In_4+
In_4-
Out_4-
Out_4+
Out_3-
Out_3+
Out_2-
Out_2+
Out_1-
Out_1+
GND
Description
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to ASIC (inside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Bidrectional Clamp to Connector (outside system)
Ground return to shield
Ordering Information
PART NUMBERING INFORMATION
PIN
16
PACKAGE
TDFN-16
LEAD-FREE FINISH
CM1236
-08DE
Part Marking
CM1236-08
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2009 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 02/24/09
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Fax: 408.263.7846
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CM1236
Specifications
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Operating Temperature Range
Storage Temperature Range
Breakdown Voltage (Positive)
RATING
-40 to +85
-65 to +150
6
UNITS
°C
°C
V
*Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL PARAMETER
V
IN
I
IN
I
F
V
ESD
I/O Voltage Relative to GND
Continuous Current through signal pins (IN
to OUT) 1000 Hr
Channel Leakage Current
ESD Protection - Peak Discharge Voltage
at any channel input, in system:
Contact discharge per IEC 61000-4-2
Standard
Residual ESD Peak Current on RDUP
(Resistance of Device Under Protection)
Channel Clamp Voltage
(Channel clamp voltage per
IEC 61000-4-5 Standard)
Positive Transients
Negative Transients
Dynamic Resistance
Positive Transients
Negative Transients
Differential Impedance
CONDITIONS
MIN
-0.5
TYP
MAX
5.5
UNITS
V
mA
100
T
A
= 25°C; V
N
= 0V, V
TEST
= 5V
±0.1
±1.0
µA
T
A
= 25°C; Note 2
IEC 61000-4-2 8kV;
RDUP = 5Ω, T
A
= 25°C;
Note 2
I
PP
= 1A, T
A
= 25°C,
t
P
= 8/20
μ
S;
Note 2
±8
3.0
kV
A
I
RES
V
CL
+9.2
-1.6
0.6
0.5
97
107
V
V
Ω
Ω
Ω
R
DYN
I
PP
= 1A, T
A
= 25ºC,
t
P
= 8/20
μ
S;
Note 2
TDR excursion from 100Ω
characteristic impedance trans-
mission line;
TR = 200ps; Note 2
Z
TDR
Zo
Differential Channels pair characteristic
impedance
Channel-to-Channel Impedance Match (Dif-
ferential)
T
R
= 200ps;
Note 2
T
R
= 200ps; T
A
= 25ºC;
Note 2
100
Ω
ΔZo
2
%
Note 1: All parameters specified at T
A
= –40°C to +85°C unless otherwise noted.
Note 2: This parameter is guaranteed by design and verified by device characterization
© 2009 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 02/24/09
●
Fax: 408.263.7846
●
www.cmd.com
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