IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO™
64 x 1, 256 x 1, 512 x 1
®
CMOS SINGLE BIT SyncFIFO
64 X 1, 256 x 1, 512 x 1
™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRELIMINARY
IDT72423
IDT72203
IDT72213
Integrated Device Technology, Inc.
FEATURES:
64 x 1-bit organization (IDT72423)
256 x 1-bit organization (IDT72203)
512 x 1-bit organization (IDT72213)
10 ns read/write cycle time (IDT72423/72203/72213)
Independent read and write clock lines
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be programmed to any depth via a dedicated port (Pn).
These flags default to Empty+7 and Full-7, respectively.
• Output enable puts output data bus in high impedance
state
• Available in 24-pin SOIC, 24-pin plastic DIP (300 mil.),
and 24-pin ceramic DIP (300 mil.)
• Military product compliant to MIL-STD-883, Class B
Advanced submicron CMOS technology
•
•
•
•
•
•
•
DESCRIPTION:
The IDT72423/72203/72213 SyncFIFO
™
are very high-
speed, low-power First-In, First-Out (FIFO) memories with a
word width of 1 and clocked read and write controls. The
IDT72423/72203/72213 have a 64, 256, and 512 x 1-bit
memory arrays, respectively. These FIFOs are appropriate
for a wide variety of serial data buffering needs, especially
telecommunications applications such as networks, modems,
signal processing, and serial interfaces.
These single-bit FIFOs have 1-bit input (D) and output ports
(Q).The input port is controlled by a free-running clock (WCLK),
and two write enable pins (
WEN1
, WEN2). Data is written into
the Synchronous FIFO on every rising clock edge when the
write enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and a read enable pin (
REN
). The
read clock can be tied to the write clock for single clock
operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (
OE
) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (
EF
)
and Full (
FF
). Two programmable flags, Almost-Empty (
PAE
)
and Almost-Full (
PAF
), are provided for improved system
control. The programmable flags default to Empty+7 and Full-
7 for
PAE
and
PAF
, respectively. The programmable flag
offset is loaded via the Program Inputs (P0 - P7), on the rising
WCLK when the load pin (
LD
) is asserted.
The IDT72423/72203/72213/ are fabricated using IDT’s
high-speed submicron CMOS technology. Military grade prod-
uct is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
P
0
- P
7
FUNCTIONAL BLOCK DIAGRAM
WCLK
D
WEN1
LD
WEN2
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 1
256 x 1
512 x 1
FLAG
LOGIC
EF
PAE
PAF
FF
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
RESET LOGIC
OUTPUT REGISTER
RCLK
RS
REN
3111 drw 01
OE
Q
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc
MAY 1994
DSC-2065/-
5.04
1
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO™
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
P
5
P
4
P
3
P
2
P
1
P
0
1
2
3
4
5
6
7
8
9
10
11
12
DIP/SOIC
TOP VIEW
P24-1
D24-1
SO24-2
24
23
22
21
20
19
18
17
16
15
14
13
P
6
P
7
D
RS
WEN1
WCLK
WEN2/
LD
V
CC
Q
PAF
PAE
V
SS
NC
RCLK
REN
FF
EF
OE
3111 drw 02
PIN DESCRIPTIONS
Symbol
D
RS
Name
Data Input
Reset
WCLK
Write Clock
Write Enable 1
WEN1
WEN2/
LD
Write Enable 2/
Load
P
0
-P
7
Q
RCLK
Program Inputs
Data Output
Read Clock
Read Enable 1
Output Enable
Empty Flag
REN
OE
EF
PAE
PAF
FF
Programmable
Almost-Empty
Flag
Programmable
O
Almost-Full Flag
Full Flag
O
Power
Ground
I/O
Description
I
Input for serial data.
I
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after
power-up.
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
I
If the FIFO is configured to have programmable flags,
WEN1
is the only write enable pin.
When
WEN1
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables,
WEN1
must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the
FF
is LOW.
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD
is HIGH at reset, this pin operates as a second write enable. If WEN2/
LD
is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,
WEN1
must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the
FF
is LOW. If the FIFO is config-
ured to have programmable flags, WEN2/
LD
is held LOW to write or read the programmable flag
offsets.
I
Offsets for the programmable flag registers are entered at these inputs on the rising edge of
WCLK when
LD
and
WEN
are LOW
O Output for serial data.
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN
is asserted.
I
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF
is LOW.
I
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a
high impedance state.
O When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
O When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7.
PAE
is synchronized to RCLK.
When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7.
PAF
is synchronized to WCLK.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is
HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
One +5Volt power supply pin.
One 0Volt ground pin.
3111 tbl 01
V
CC
GND
5.04
2
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO™
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CCM
V
CCC
Parameter
Military Supply Voltage
Commercial
Supply Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Min.
4.5
4.5
0
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
3111 tbl 03
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +135
50
°C
°C
°C
mA
GND
V
IH
V
IH
V
IL
NOTE:
3111 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
3111 tbl 04
NOTES:
1. With output deselected (
OE
= HIGH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= -55°C to +125°C)
IDT72423
IDT72203
IDT72213
Commercial
t
CLK
= 10, 12, 15ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
1
10
—
0.4
80
IDT72423
IDT72203
IDT72213
Military
t
CLK
= 15, 25ns
Min.
Typ.
Max.
–10
–10
2.4
—
—
—
—
—
—
—
10
10
—
0.4
100
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= -2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Unit
µA
µA
V
V
mA
3111 tbl 05
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
3. Measurements are made with outputs unloaded. Tested at f
CLK
= 20MHz.
5.04
3
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO™
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to + 70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Commmercial
72423L10
72203L10
72213L10
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
AF
t
AE
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse
Width
(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(2)
Output Enable to Output Valid
Output Enable to Output in High-Z
(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Skew time between Read Clock &
Write Clock for Empty Flag &Full Flag
Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
Min.
100
2
10
4.5
4.5
3
0
3
0
10
10
10
10
0
3
3
7.5
7.5
7.5
7.5
5
22
Max.
—
7.5
—
—
—
—
—
—
—
—
—
—
—
—
6.5
6.5
—
—
—
—
—
—
72423L12
72203L12
72213L12
Min.
—
2
12
5
5
3
0
3
0.2
12
12
12
––
0
3
3
—
—
—
—
5
22
Max.
83.3
8
—
—
—
—
—
—
—
—
—
—
12
—
7
7
8
8
8
8
—
—
Com'l & Mil.
72423L15
72203L15
72213L15
Min.
—
2
15
6
6
4
1
4
1
15
15
15
—
0
3
3
—
—
—
—
6
28
Max.
66.7
10
—
––
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
—
3
25
10
10
6
1
6
1
25
25
25
—
0
3
3
—
—
—
—
10
40
Military
72423L25
72203L25
72213L25
Min.
Max.
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3111 tbl 06
5V
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
3111 tbl 07
1.1KΩ
D.U.T.
680Ω
30pF*
3111 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.04
4
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO™
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS
:
Data In (D)
— Input for serial data.
CONTROLS:
Reset (
RS
)—Reset
is accomplished whenever the Reset
(
RS
) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (
FF
) and Programmable Almost-Full Flag
(
PAF
) will be reset to HIGH after t
RSF
. The Empty Flag (
EF
) and
Programmable Almost-Empty Flag (
PAE
) will be reset to low
after t
RSF
. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK)—A
write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data set-
up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (
FF
) and
Programmable Almost-Full Flag (
PAF
) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or coinci-
dent.
Write Enable 1 (
WEN1
)—If
the FIFO is configured for
programmable flags, Write Enable 1 (
WEN1
) is the only
enable control pin. In this configuration, when Write Enable 1
(
WEN1
) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (
WEN1
) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (
FF
) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
FF
) will go high after tWFF,
allowing a valid write to begin. Write Enable 1 (
WEN1
) is
ignored when the FIFO is full.
Read Clock (RCLK)
— Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (
EF
) and Programmable Almost-Empty Flag (
PAE
)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or coinci-
dent.
Read Enables (
REN
)—When
the Read Enable (
REN
) is
LOW, data is read from the RAM array to the output register
on the LOW-to-HIGH transition of the read clock (RCLK).
When the Read Enable (
REN
) is HIGH, the output register
holds the previous data and no new data is allowed to be
loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (
EF
) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (
EF
) will go HIGH after t
REF
and a valid read can begin.
The Read Enable (
REN
) is ignored when the FIFO is empty.
Output Enable (
OE
)—When
Output Enable (
OE
) is en-
abled (LOW), the output buffer receives data from the output
register. When Output Enable (
OE
) is disabled (HIGH), the Q
data output is in a high-impedance state.
Write Enable 2/Load (WEN2/
LD
)—This
is a dual-purpose
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth expan-
sion. If Write Enable 2/Load (WEN2/
LD
) is set HIGH at Reset
(
RS
= LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (
WEN1
) is LOW and Write Enable 2/Load
(WEN2/
LD
) is HIGH, data can be loaded into the input register
and RAM array on the LOW-to-HIGH transition of every write
clock (WCLK). Data is stored in the RAM array sequentially
and independently of any on-going read operation.
In this configuration, when Write Enable (
WEN1
) is HIGH
and/or Write Enable 2/Load (WEN2/
LD
) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (
FF
) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
FF
) will go HIGH after t
WFF
,
allowing a valid write to begin. Write Enable 1 (
WEN1
) and
Write Enable 2/Load (WEN2/
LD
) are ignored when the FIFO
is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/
LD
) is set LOW at Reset (
RS
= LOW). The IDT72423/72203/72213 devices contain four 8-
bit offset registers which can be loaded with data on the
Program Inputs (P
0
- P
7
). See Figure 3 for details of the size
of the registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (
WEN1
) and Write Enable 2/Load (WEN2/
LD
) are set LOW, data on the Program Inputs (P
0
- P
7
) are
written into the Empty (Least Significant Bit) offset register on
the first LOW-to-HIGH transition of the write clock (WCLK).
Data is written into the Empty (Most Significant Bit) offset
register on the second LOW-to-HIGH transition of the write
clock (WCLK), into the Full (Least Significant Bit) offset
register on the third transition, and into the Full (Most Signifi-
cant Bit) offset register on the fourth transition. The fifth
transition of the write clock (WCLK) again writes to the Empty
(Least Significant Bit) offset register.
5.04
5
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