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CD40106BFMSR

产品描述HEX 1-INPUT INVERT GATE, CDIP14, FRIT SEALED, DIP-14
产品类别逻辑    逻辑   
文件大小77KB,共9页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
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CD40106BFMSR概述

HEX 1-INPUT INVERT GATE, CDIP14, FRIT SEALED, DIP-14

CD40106BFMSR规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码DIP
包装说明DIP, DIP14,.3
针数14
Reach Compliance Codenot_compliant
JESD-30 代码R-GDIP-T14
JESD-609代码e0
长度9.585 mm
负载电容(CL)50 pF
逻辑集成电路类型INVERTER
最大I(ol)0.00036 A
功能数量6
输入次数1
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装等效代码DIP14,.3
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)NOT SPECIFIED
电源5/15 V
Prop。Delay @ Nom-Sup378 ns
传播延迟(tpd)378 ns
认证状态Not Qualified
施密特触发器YES
筛选级别MIL-PRF-38535 Class V
座面最大高度5.33 mm
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
总剂量100k Rad(Si) V
宽度7.62 mm
Base Number Matches1

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CD40106BMS
December 1992
CMOS Hex Schmitt Triggers
Pinout
CD40106BMS
TOP VIEW
A 1
G=A 2
B 3
H=B 4
14 VDD
13 F
12 L = F
11 E
10 K = E
9 D
8 J=D
Features
• High Voltage Type (20V Rating)
• Schmitt Trigger Action with No External Components
• Hysteresis Voltage (Typ.)
- 0.9V at VDD = 5V
- 2.3V at VDD = 10V
- 3.5V at VDD = 15V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Low VDD to VSS Current During Slow Input Ramp
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
C 5
I=C 6
VSS 7
Functional Diagram
A
1
2
G=A
B
3
4
H=B
Applications
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
C
5
6
I=C
D
9
8
J=D
E
11
10
K=E
• Astable Multivibrators
Description
CD40106BMS consists of six Schmitt trigger circuits. Each
circuit functions as an inverter with Schmitt trigger action on
the input. The trigger switches at different points for positive
and negative going signals. The difference between the
positive going voltage (VP) and the negative going voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 17).
The CD40106BMS is supplied in these 14 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
*
F
13
12
L=F
Logic Diagram
A
1 (3, 5, 9, 11, 13)
*
*
G
2 (4, 6, 8, 10, 12)
VDD
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. 1 OF 6 SCHMITT TRIGGERS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3354
7-1327

 
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