CD4042B Typ
s
COS/MOS
Quad Clocked
"0"
Latch
High-Voltage Types (20-Volt Rating)
The RCA-CD40428 types contain four latch
circuits, each strobed by a common clock.
Complementary buffered outputs are availa-
ble from each circuit. The impedance of the
n- and p-channel output devices is balanced
and all outputs are electrically identical.
I nformation present at the data input is
transferred to outputs Q and
Q
during the
CLOCK level which is programmed by the
POLARITY input. For POLARITY
=
0 the
transfer occurs during the 0 CLOCK level
and for POLARITY
=
1
the transfer occurs
during the
1
CLOCK level. The outputs
follow the data input providing the CLOCK
and POLARITY levels defined above are
present. When a CLOCK transition occurs
(positive for POLARITY
=
0 and negative
for PO LAR ITY
=
1)
the information present
at the input during the CLOCK transition is
retained at the outputs until an opposite
CLOCK transition occurs.
\
The CD40428 types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D
and F suffixes). 16-lead dual-in-line plastic
package
(E
suffiX), 16-lead ceramic flat
package
(K
suffix), and
In
chip form
(H
suffix).
Features:
• Clock polarity control
• a
and () outputs
• Common clock
• Low power TTL compatible
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1p.A at 18 V over
full package-temperature range; 100 nA at
18 V and 25
0
C
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package
temperature range):
1 Vat VDD
=
5 V
2 V at VDD
=
10 V
2.5 Vat VDD
=
15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
0,
0,
0,
02
°2
03
13
04
CLOCK
5
()..--_.r-"
POLARITY
6(')...-........
-~)
voo~
vsser!-
CD4042B
FUNCTIONAL DIAGRAM
04
QI
I.
2
Ie
15
voo
04
D4
ill
Applications:
•
•
•
Buffer storage
Holding register
General digital logic
III
CLOCK
POLAIITY
02
Vss
TOP VIEW
14
III
12
II
Dli
OS
Oll
Q2
10
9
li2
9:ZCS-20~RI
TERMINAL ASSIGNMENT
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
CHARAC-
TERISTIC
~~c~o~N~e~IT~I=O~N=S~4-
__
~r=~~~~~~~~~~~~--4UNITS
Vo
Vee
(V)
(V)
QUiescent
DeVice
(ONE OF FOURlATCHE 5 -,
I
Cl
p.A
.,
I
L ___
c1... _ _ _
.J
rnA
noc,
0
.:
i""I:t~t:~,i
p
I
Current,
IOH Min
Output Volt-
age'
Low-Level.
VOL Max.
Output Volt·
age:
High- Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
I
I
TG
Cl
l'
I
I
I
I
POlAR'TY~;
I
I
L ____________
...J
g
0
0
V
VDD
*
ALL INPuTS ARE
PROTECTED BY
COS/MOS PROTECTION
NETWORK
VSS
CLOCK
0
POLARITY
a
D
LATCH
D
LATCH
V
...r
1
~
1
1
0,18
18
±10-5 ±0.1
p.A
164 ____________________________________________________________________
FIg.
1 -
LogIc block diagram and
truth table.
CD4042B Typ
s
MAXIMUM RATINGS,
Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V OO )
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER OISSIPATION PER PACKAGE (PO):
For T A • -40 to +60 o C (PACKAGE TYPE E)
. . . . . . • ..
500mW
For T A
~
+60 to +85
0
C (PACKAGE TYPE E)
. .
Derate Linearly at 12 mW/oC to 200 mW
For TA " -55 to +100
0
C (PACKAGE TYPES 0, F)
. . . . . . . ..
500mW
For TA" +100 to +125
0
C (PACKAGE TYPES 0, F)
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUTTRANSISTOR
FOR T A" FULL PACKAGE· TEMPERATURE RANGE (All PElckage Types)
100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +125
0
C
PACKAGE TYPE E .
-40 to +85
0
C
STORAGE TEMPERATURE RANGE (T stg )
-65 to +150
0
C
LEAD TEMPERATURE (DURING SOLDERING).
.
At distance 1/16
±
1/32
Inch (1.59
±
0.79 mm) from case for 11) s max.
~
I
ORAIN-TO-SOURCE VOlTAGE (Vosl-V
Fig.
2 -
Typical output low (sink) current
characteT/stics.
RECOMMENDED OPERATING CONDITIONS at T A = :Z5°C, Except as Noted.
For maximum reliability, nominal operating conditions should
be
selected so that
operation is always within the following ranges:
CHARACTER ISTIC
VOD
(V)
LIIVIITS
ALL TYPES
Min.
Max.
UNITS
I
I~
Supply-Voltage Range
(For T A=Full Package
Temperature Range)
Clock Pulse Width, tw
-
5
10
15
5
10
15
5
10
15
5,10
15
3
18
V
ORAIN-TO-SOURCE \/OlTAGE (Vos'-V
200
100
60
50
30
25
120
60
50
-
-
-
ns
Fig.
3 -
Minimum output low (sink) current
charactertstlcs.
Setup Time,
ts
Hold Time, tH
Clock Rise or Fall
Time: tr ' tf
-
-
-
-
-
-
ns
ORAIN-TO-SOURCE VOLTAGE (Vos'-V
ns
Not 'Ise or fall
time sensitive.
JlS
Fig.
4 -
TYPical output high (source)
current characteristics.
ORAIN-TO-SOURCE VOLTAGE IVOSI-V
I~
1-:.17~
I·..
BIENT
'TA'
r~
,'.'
H+
I~
;
I
LOAD CAPACITANCE (el' -
pF
LOAD CAPACITANCE (el) -
pF
~
Fig.
5 -
Minimum output high (source)
current characteT/stlcs.
Fig.
6 -
TYPical propagation delay time vs.
load capacitance-data to
Q.
Fig.
7-
Typical propagation delay time vs.
load capacitllnce-data
to
Q.
______________________________________________________________________ 165
II
CD4042B Typ
s
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
=
25°C; Input t"
1f
=
20 ns, CL
=
50 pF,
RL =200
Kn
LIMITS
ALL TYPES
Typ.
110
65
40
150
75
60
226
100
80
250
115
90
100
50
40
100
50
30
60
30
25
0
0
0
Max.
220
110
80
300
150
100
460
200
160
500
230
180
200
100
80
200
100
60
120
60
50
50
30
25
UNITS
CHARACTERISTIC
Propagation Delay
Time: tpHL' tpLH
Data In to
Q
Data In to
Q
VDD
(V)
6
10
16
5
10
16
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5,10
15
ns
ns
lOAD CAPACITANCE (Cli -
pF
Clock to
Q
ns
Fig.
8 -
Typical propagation delay time vs.
load capacitance-clock
to
Q
Clock to
a
ns
Transition
Time: tTHL' tTLH
Minimum Clock
Pulse Width, tw
ns
ns
Minimum Hold Time, tH
Minimum Setup
Time, ts
Clock Input Rise or Fall
Time: t r, tf
Input Capacitance, CI N
(Any Input)
ns
ns
lOAD CAPACITANCE (Cl I -
of
II'S.
Not rise or fall
time sensitive.
,..s
pF
Fig.
9 -
'Typical propagation delay time
load capacitance-clock
to
0.
-
5
7.5
10'
AMBIENT TEMPERATURE CTA
.-Z!5·C
NOT[ I
CLg,CK
1
----==-=--o~.-------
NOTE 2
._
LOAD CAPACITANCE
CL-'!5pF
C
.~pF
IN~
DATA
=!
{
~
I
I
I
I
~--+---------
10'
10.
10 0
10'
lOAD CA"'CITANC[ (Cll-p'
INPUT FR[QUENCY-Kz
j-ISTIH-I
I
I
I.
Fig. 10
-
Typical power dissipation
frequency.
v,.
Fig.
"
-
Typical transition time
capacitance.
II'S.
load
OUTPUT
INPUTS
INPUTQVDO
OUTPUTS
o
Vss
o
VC
V~l
DO
VSS
--!@
J
NOTE
NOTES.
I
FOR
POStnVf:
CI.OCK
tDGE.INPUT
DATA
IS LATCHED WHEN
POLAIIITY IS LOW
Z _
NEDATIVE CLOCK EDGE. INPUT DATA IS LATCHED WHEN
POLARITY IS HIGH
,2CS·Z7ISO
~~'TN~"UW~j8(NAT(ON
Vss
Fig.
13 -
QUIescent d8Vlce current test circuit.
Fig.
74 -
Input voltage testcircuir.
Fig.
12 -
Dynllmic telt ptlramet8n.
166 _________________________________________________________________________
CD4042B Typ
s
V~~NPU(J' :::~~ ,,~,
'00
o
~
Vss
SEOUENTIALLY.
TO 80TH Voo AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS
VSS
Fig
75-
Input current test CircUit.
Chip Photograph, Dimensions, and Pad layout
e
I
D,ml'ns,ons In parentheses are In millimeters and
are denved from the basIc Inch dimensions as In-
d,caled Gnd graduations are In mtls
(70-
3 Inch)
The photographs and dimensions of each CDS/MDS
chip represent a chip when
It IS
part of the wafer
Whell the
w~fer
IS
cut Into ChiPS, the cleavage
o
anglE's are
57
Instead of 90 With respect to the
face of the chip Therefore, the Isolated chip
IS
actu.,lIv
7
mtls (0
17
mm) larger In both dimensions.
______________________________________________________________________ 167
stm32/stm8
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