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JUNE 1995
PRELIMINARY INFORMATION
DS3984 - 3.4
MV6640
POCSAG DECODER
The MV6640 POCSAG decoder is capable of operating at
512 or 1200 baud. This device together with a suitable
receiver, provides the major components for a POCSAG
pager.
POCSAG is the acronym for Post Office Code
Standardisation Advisory Group. The POCSAG code is the
most accepted radio paging standard, (CCIR RPC No.1) and
provides for over 2 million pager IDs, four of which may be held
in this device. The POCSAG code format is shown in Fig. 3.
The design is optimised for very low power, low voltage
use. Advanced features allow the decoder to be used in a wide
range of applications.
The pinout and architecture are shown in Figs. 1 and 2.
FEATURES
Low voltage supply (1V min, 3.5V max)
Low current consumption (Typically 15µA)
Voltage doubler for radio receiver or µP and Display
True 2 bit CRC error correction with error status
indication
Tone only and/or messaging pager at 512
or 1200 baud using a single 32768Hz crystal
Silent call storage
Directly drives tone transducer
Programmable tone generator output frequency
(2048 or 2731 Hz)
Interface to SL6609A radio receiver chip
Low battery alert
Interface to Standard 3 wire EEPROM
True or Inverted data
NP28
Fig. 1 Pin Connection
(top view - not to scale)
APPLICATIONS
Wrist watch pager
Message display pager
Tone only pager
Data receivers
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD2 - GND)
Voltage on any pin
Operating temperature
Storage temperature
-0.5V to 5V
-0.3V to VDD2 + 0.3V
-20°C to + 70°C
-55°C to +125°C
ORDERING INFORMATION
MV6640/KG/NPDS
MV6640/KG/NPDE
-
-
devices in anti-static sticks
devices in tape & reel
Fig. 2 MV6640 Block Diagram
MV6640
Pin Description.
Pin No
1
2
3
4
5
6
7
8
Pin Name
DIN
DV
RDATA
RCLK
RCS
DS
DO
RESET
Pin Description
Serial data input to the device. Inverted or non-inverted POCSAG code at 512 or 1200
baud. Polarity and data rate programmable.
Data Valid output high indicates that a valid message is being received.
It can be used as a 'wake up' signal for a micro controller.
Bi-directional data port for reading in the EEPROM data to internal memory.
High Impedance when not in use.
Data Clock output for the EEPROM interface. High impedance when not in use.
Chip select for external EEPROM. High impedance when not in use. Active High.
Data Strobe. This output goes active high prior to each bit of valid message data being
transmitted on DO.
Data Output. Valid address and message data is output on this pin.
This pin is used to activate the power on reset circuit. A capacitor between this pin
and GND sets the reset time when powered up. The device may also be externally
reset from this input.
Alert in. One of two inputs to the tone generator circuit. This input when high produces a
continuous tone at the two tone outputs.
Battery level output. This goes high if battery level input (BLI) is high for 8ms.
If no preamble or sync word is detected for 60 batches, the range output goes high.
Decoder is switched ‘ON’ by holding this pin high.
Pulsed high to cancel tones or replay calls.
Decoder is switched to ‘MEM’ (memory or 'silent' mode) by holding this pin high.
Visual alert. Pulses high to indicate incoming call when in silent mode.
Can be used to drive an LED.
Test input active high. Hold low during normal operation.
The beep codes and alerts are output on this pin. The output configuration and
tone output frequencies are programmable.
The beep codes and alerts are output on this pin. The output configuration and
tone output frequencies are programmable.
Output to external bipolar vibrator driver when in silent mode.
Crystal oscillator output.
Crystal oscillator input.
Negative supply input.
Positive supply, doubled if voltage doubler active, otherwise connected to VDD1.
Positive supply input (1V min).
Connect external inductor and diode for voltage doubler if required.
Test input. Held low for normal operation.
Receiver Enable. This output when low powers down or disables the receiver to save
power.
Battery level input from receiver. Normally tied low. The high level indicates battery
flat and triggers a tone if high for 8ms.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AIN
BLO
RANGE
ON
REPLAY
MEM
VA
TSTEN
TO2
TO1
VIB
X2
X1
GND
VDD2
VDD1
LD
TSTIN
RE
BLI
DECODER APPLICATIONS
The MV6640 can be used in either a “Tone Only” or a “Tone and Message” pager. When used in tone only applications, the
only additional IC requirements are a receiver (such as the SL6609A) and a small EEPROM (primarily for holding the pager
identification). A full tone and message pager can be implemented with the addition of a simple microprocessor/LCD driver.
OPERATION
On power up the MV6640 reads four addresses and other set-up information from the EEPROM. It then enables the receiver
and searches the incoming data for a sync code word. Once sync. has been achieved the MV6640 will power down the receiver
except for those periods when valid data is expected. When the receiver is enabled, the incoming data is searched for the
expected addresses.
When a valid address is detected the MV6640 activates external indicators to alert the user. Data Valid goes high and the
Data Output DO shows which address has been received, the function bits and the error status. If the address is followed by a
message this is also output on DO. When the message has finished the MV6640 returns to searching for a valid address.
2
MV6640
THE POCSAG CODE
A transmission of POCSAG code consists of at least 576
bits of preamble, i.e. alternate 1010s, followed by batches of
codewords, each batch starting with a synchronisation
codeword (SC) followed by 8 frames of data. (see Fig. 3a).
Each frame consists of 2 codewords, where the pager ID’s
3 least significant bits correspond to the frame number in the
batch.
Each codeword consists of 32 bits as shown in Fig. 3b.
There are two types of codeword, address and message. The
SC and IC are special cases of address codewords. Bits 20-
21 of the address codeword transmitted determine the tone
cadence pattern to be output by the decoder.
Message codewords immediately follow their particular
address and are only displaced by the SC. An idle codeword
(IC) is transmitted in the absence of an address or message
codeword. In a message sequence, the end of the message
is denoted by another address or idle codeword.
Signal Format
Preamble
SC 0
Batch Format
Frames 0 to 7 (000 to 111)
1 Frame contains 2 CODEWORDS
(a)
Address CODEWORD (A/B)
1
FLAG BIT=0
2-19
18 Address BITS
20-21
FC1 FC2
22-31
Check BITS
32
Parity BIT
1
2
1st Batch
3
4
2nd Batch 3rd Batch
5
6
7 SC 0
1
Message CODEWORD (M)
1
FLAG BIT=1
2-21
20 Message BITS
22-31
Check BITS
32
Parity BIT
SYNC CODEWORD (SC)
0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0
IDLE CODEWORD (IC)
0 1 1 1 1 0 1 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1
(b)
MESSAGE FORMAT
DATA IN
DATA OUT
A
M
A
M
M
SC
M
M
IC
M
IC
B
M
B
M
M
A
M
IC
A
IC
IC
Stop
Message
Message for 'A'
Start
Message
for 'A'
Message for 'B'
Start
Stop
Message Message
for 'B'
for 'A'
Stop
Message
for 'B"
Start next
Message (No
DATA Sent)
(c)
Fig. 3 POCSAG Data Format
3
MV6640
ACCESSING THE EEPROM
The decoder initiates an EEPROM read by taking the chip
select (RCS) high. The EEPROM clock (RCLK) and data
(RDATA) outputs become active and a “Read starting at
address 0” instruction is output. The instruction is clocked into
the EEPROM on the positive edge of RCLK. Eighty five bits
of data are then clocked out of the EEPROM on the positive
edge of RCLK and sampled by the MV6640 on the negative
edge.
Note that the EEPROM must be a 1k bit device with three
wire interface that supports sequential read. Suitable
EEPROMs include the Exel XL93C46, Microchip 93AA46 and
the SII S-2913. The EEPROM should be configured as 16-bit
organisation.
The first eighteen bits of data are address A1, in the same
order as they are transmitted in the POCSAG code. The next
eighteen bits are address A2 in the same order followed by
three bits defining which frame of the POCSAG signal will be
checked for addresses A1 and A2. The next thirty nine bits are
addresses and frame B1 and B2 in the same order as above.
Function Bit
FB1
Data rate select
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
Feature
1200 baud.
512 baud.
Disabled.
Enabled.
Enabled.
Disabled.
Enabled.
Disabled.
2048Hz.
2731Hz.
Two Tone Levels.
Single Tone Level.
No Inversion.
Inversion.
The last seven bits are used to configure the decoder. The
baud rate, voltage doubler, silent override, tone generation
and data polarity can be programmed as in Fig. 4.
The function of each bit loaded from the EEPROM is
described in Fig. 17.
The EEPROM data is loaded 3 seconds after power up or
an external reset. The delay allows the voltage doubler to
attain its correct voltage. The data is reloaded when the
decoder is switched from STANDBY to ON or MEM modes as
above but without the 3 second delay as the voltage doubler
will already have reached its correct output voltage.
The RCS, RCLK and RDATA pins default to high
impedance state when the MV6640 is not accessing the
EEPROM. This allows other devices to share the EEPROM
(eg a microcontroller). To prevent the signals floating the pins
have pull-down resistors (50kΩ nominal) which are disabled
when the EEPROM chip select goes high.
If only one address is required all four addresses should be
programmed with the same data; both sets of frame position
bits should be identical and FB3 and FB4 the same. The
address code output from DO will be B2.
If two addresses are required A1 and A2 should both
contain copies of one of them and B1 and B2 the other. The
address output code will be A2 or B2 respectively.
If three addresses are required then either A1 and A2 or B1
and B2 should contain duplicate copies of the same data. The
address output will be A2 in the former case or B2 in the latter.
The address codes output on D0 are shown in Fig. 8.
The silent overide facility is only available for addresses A1
and B1. If A1 and A2 are the same the overide facility is
available and similarly if B1 and B2 are the same.
FB2
Voltage Doubler
FB3
Silent Override A1
FB4
Silent Override B1
FB5
Tone Frequency
FB6
FB7
Tone Configuration
Input Data polarity
POCSAG CODE SYNCHRONISATION
After the decoder has been powered up and the EEPROM
read completed, synchronisation to the incoming POCSAG
data is performed. Once bit synchronisation is achieved by the
clock recovery circuit, the data stream is checked bitwise for
the sync codeword (SC).
Fig. 4 Function Bit Allocation
Fig.5 EEPROM interface
4
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