FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20881-3E
FLASH MEMORY
CMOS
32M (4M
×
8/2M
×
16) BIT
Dual Operation
MBM29DL32XTE/BE
-80/90/12
s
DESCRIPTION
The MBM29DL32XTE/BE are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M
words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V
V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also be
reprogrammed in standard EPROM programmers.
MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which can be considered to be two
separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is
simultaneously taking place on the other bank.
(Continued)
s
PRODUCT LINE UP
Part No.
V
CC
= 3.3 V
Ordering Part No.
V
CC
= 3.0 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
+0.3 V
–0.3 V
+0.6 V
–0.3 V
MBM29DL32XTE/BE
80
—
80
80
30
—
90
90
90
35
—
12
120
120
50
s
PACKAGES
48-pin plastic TSOP (I)
Marking Side
48-pin plastic TSOP (I)
63-ball plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-63P-M01)
MBM29DL32XTE/BE
-80/90/12
)
(Continued)
In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable
(OE) controls.
The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
Typically, each sector can be programmed and verified in about 0.5 seconds.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the
factory.
Internally generated and regulated voltages are provided for the program and erase operations. A low V
CC
detector
automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ
7
, by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase
cycle has been completed, the devices internally reset to the read mode.
The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously
via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
2
MBM29DL32XTE/BE
-80/90/12
s
FEATURES
• 0.23
µm
Process Technology
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
63-ball FBGA (Package suffix: PBT
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
Eight 4K word and sixty-three 32K word sectors in word mode
Eight 8K byte and sixty-three 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
• Embedded Erase
TM
*Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
*:
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
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