AN2133
APPLICATION NOTE
LIS3L02DQ
3-Axis -
±2g
DIGITAL OUTPUT LINEAR ACCELEROMETER
This document is intended to provide application note for the 3-axis digital output linear MEMS
accelerometer provided in QFN-44 package.
1 Description
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The LIS3L02DQ is a tri-axis digital output linear accelerometer that includes a sensing element
and an IC interface able to take the information from the sensing element and to provide the
measured acceleration signals to the external world through an I
2
C/SPI serial interface.
The sensing element, capable to detect the acceleration, is manufactured using a dedicated
process developed by ST to produce inertial sensors and actuators in silicon.
The IC interface instead is manufactured using a CMOS process that allows high level of inte-
gration to design a dedicated circuit which is factory trimmed to better match the sensing ele-
ment characteristics.
The LIS3L02DQ has a full scale of
±2g
and it is capable of measuring accelerations over a
maximum bandwidth (@ -3dB) of 1120 Hz for the X, Y and Z axes. The device bandwidth may
be selected according to the application requirements. A self-test capability allows the user to
check the functioning of the system.
The device may be configured to generate an inertial wake-up interrupt signal when a pro-
grammable acceleration threshold is exceeded along one of the three axes.
The LIS3L02DQ is specified over a temperature range extending from -20°C to +70°C and it
is provided in a plastic Quad Flat No-lead (QFN) package. This is a leadless package based
on copper lead frame which exploits half-encapsulation technology to expose the rear side of
the die pad and the tiny fingers for the connection with the PCB.
The small size and weight of this package make it an ideal choice for handheld portable appli-
cations such as cell phones and PDAs or any other application where size, weight and pack-
age performance are required.
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Rev. 1
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AN2133 APPLICATION NOTE
2 Electrical Connection
The typical electrical connection of the LIS3L02DQ is shown in Figure 1.
Figure 1. LIS3L02DQ ELECTRICAL CONNECTION
PACKAGE SEEN FROM THE TOP
X
Vdd
Y
1
GND
10µF
GND
100nF
GND
LIS3L02DQ
Z
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
GND
Vdd
Vdd_IO
GND
Vdd_IO
: Digital signal from/to system controller. Signal’s levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line (Vdd typ=3.3V) while the I/O pads are supplied
through Vdd_IO.
Both the voltage supplies must be present at the same time to have proper behavior of the IC.
The exposed pad must be left unconnected.
The functionality of the device and the measured acceleration data are selectable/accessible
through the I
2
C/SPI interface. When using the I
2
C, CS must be tied high while SDO must be
left floating.
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SDO
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SCL/SPC
CS
AN2133 APPLICATION NOTE
3 Absolute Maximum Rating
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these con-
ditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
Table 1. Absolute Maximum Rating
Symbol
Vdd
Vdd_IO
Vin
A
POW
Supply voltage
I/O pads Supply voltage
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO)
Acceleration (Any axis, Powered, Vdd=2.4V)
Ratings
Maximum Value
-0.3 to 6
-0.3 to Vdd +0.1
-0.3 to Vdd +0.3
3000g for 0.5 ms
10000g for 0.1 ms
A
UNP
Acceleration (Any axis, Unpowered)
3000g for 0.5 ms
Unit
V
V
V
10000g for 0.1 ms
T
OP
T
STG
Operating Temperature Range
Storage Temperature Range
4 Theory of Operation
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The LIS3L02DQ is a low-cost, tri-axis digital output linear accelerometer provided in a plastic
Quad Flat No-lead (QFN) package that includes a sensing element and an IC interface able
to take the information from the sensing element and to provide the measured acceleration sig-
nals to the external world through an I
2
C/SPI serial interface.
The sensing element, capable to detect the acceleration, is manufactured using a ST’s propri-
etary process which has been developed to produce silicon inertial sensors and actuators.
This technology allows to carry out suspended silicon structures which are attached to the sub-
strate in a few points called anchors and free to move on a plane parallel to the substrate itself.
To be compatible with the traditional packaging techniques a cap is placed on top of the sens-
ing element to avoid blocking the moving parts during the molding phase of the plastic encap-
sulation.
When a linear acceleration is applied, the proof mass displaces from its nominal position,
causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge
integration in response to a voltage pulse applied to the sense capacitor.
The nominal value of the capacitors, at steady state, is in the range of few pF and when an
acceleration is applied the maximum variation of the capacitive load is up to 100 fF.
The measurement IC interface is based over a standard CMOS process thus allowing high lev-
el of integration. The complete measurement chain is composed by a low-noise capacitive am-
plifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor
and by three
Σ∆
analog-to-digital converters, one for each axis, that translate the produced sig-
nal into a digital bitstream.The
Σ∆
converters are tightly coupled with dedicated reconstruction
filters which remove the high frequency components of the quantization noise and provide low
rate and high resolution digital words. The charge amplifier and the
Σ∆
converters are operated
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AN2133 APPLICATION NOTE
respectively at 107.5 KHz and 35.8 KHz. The data rate at the output of the reconstruction de-
pends on the user selected Decimation Factor (DF) and spans from 280 Hz to 4480 Hz.
The acceleration data may be accessed through an I
2
C/SPI interface thus making the device
particularly suitable for direct interfacing with a microcontroller.
The LIS3L02DQ features a Data-Ready signal (RDY) which indicates when a new set of mea-
sured acceleration data is available thus simplifying data synchronization in digital systems.
The LIS3L02DQ may also be configured to generate an inertial wake-up interrupt signal ac-
cordingly to a programmed acceleration event along the enabled axes.
Figure 2. Device Block Diagram
S1X
S1Y
S1Z
rot
S2Z
S2Y
S2X
MUX
CHARGE
AMPLIFIER
DE
MUX
Σ∆
Reconstruction
Filter
I
2
C
CS
SCL/SPC
SDA/SDIO
SDO
Σ∆
Reconstruction
Filter
Regs
Array
SPI
Σ∆
Reconstruction
Filter
SELF-TEST
REFERENCE
TRIMMING CIRCUIT
CLOCK
&
PHASE GENERATOR
5 Power Supply and Board Layout Hints
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The LIS3L02DQ is designed for a voltage supply spanning from 2.7V up to 3.6V. The typical
current consumption in normal mode at 3.3V is 1mA.
Adequate power supply decoupling is required to ensure IC performances. The optimum de-
coupling is achieved by using two capacitors of different types that target different kinds of
noise on the power supply leads. To attenuate high frequency transients, spikes, or digital
hash on the line it is recommended to use a 100nF ceramic or polyester capacitor which must
be placed as close as possible to device Vdd lead. For filtering lower-frequency noise signals,
a larger aluminum capacitor of 10µF or greater should be placed near the device in parallel to
the former capacitor.
It is recommended that the afore capacitors are placed as close as possible to pin 4.
Due to the high sensitivity of this device maximum care must be taken during board layout to
avoid any kind of coupling between any switching signal, power supplies and grounds tracks.
Particular attention must be paid to the Vdd line which should be shielded against any source
of electromagnetic noise.
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CONTROL LOGIC
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INTERRUPT GEN.
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AN2133 APPLICATION NOTE
6 Digital Interfaces
The registers embedded inside the LIS3L02DQ may be accessed through I
2
C and SPI serial
interfaces. They are mapped onto the same pads. To select/exploit the I
2
C interface, CS line
must be tied high.
Table 2. I
2
C/SPI signals mapping
Pin Name
IF_CS
CK/SCL
SDI/SDA/SDO
Description
SPI chip select (SPE)
I
2
C/SPI selector (1: I
2
C mode; 0: SPI enabled)
SPI CK line (SPC)
I
2
C clock line (SCL)
SPI data in (SPDI)
I
2
C serial data (SDA)
SPI data out (SPDO) -when in 3-wire mode-
SPI data out (SPDO) -when not in 3-wire mode-
SDO
6.1 I
2
C Bus Interface
The LIS3L02DQ I
2
C is a bus slave. The I
2
C is employed to write/read the data into/from the
registers.
The relevant I
2
C terminology is shown in Table 3:
Table 3. Terminology
Term
Transmitter
Receiver
Master
Slave
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I
2
C bus: SCL and SDA. These pins are described
in the table below:
Table 4. I
2
C Pin Description
Term
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SCL
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Description
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Description
Serial CLock
Line
Serial DAta
Line
SDA
SDA is a bidirectional line. Both SCL and SDA are connected to a positive supply voltage via
an internal pull-up resistor. When the bus is free both lines are HIGH.
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