FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16801-1E
32-bit Proprietary Microcontroller
CMOS
FR60Lite MB91270/280 Series
MB91F272/F272S/V280
■
DESCRIPTION
The MB91270/280 series is single chip microcontroller that builds various I/O resources and the bus control
mechanisms into by using 32-bit efficient RISC CPU for the built-in control being demanded for CPU processing
high performance/high-speed. Because the vast address space that 32-bit CPU accesses is supported, the external
bus access is basically. To speed up CPU instruction execution, MB91270/280 has built-in RAM of 16 Kbytes (for
data) .
It is best specification for the built-in usage in which efficient CPU processing power such as the digital video
camera, navigation systems, and DVD players is demanded.
The MB91270/280 series power-up the bus access based on FR30/40 family CPU, and is FR60 Lite family
corresponding to use at high speed.
■
FEATURES
•
FR CPU characteristics
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency: 32 MHz (using the PLL at an oscillation frequency of 4 MHz)
• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
(Continued)
■
PACKAGES
401-pin ceramic PGA
100-pin plastic LQFP
(PGA-401C-A02)
(FPT-100P-M05)
MB91270/280 Series
• Instruction optimized for embedded applications:
Memory-to-memory transfer, bit manipulation, barrel shift instruction etc.
• Instructions adapted for high - level languages:
Function entry/exit instructions, multiple - register load/store instructions
• Register interlock functions:
Facilitating coding in assemblers
• Built-in multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles.
• Interrupt (PC, PS save): 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction compatible with FR family
•
External bus interface
• Maximum operating frequency: 16 MHz
• Can output full 24-bit address range (16 Mbyte space)
• 8,16-bit data output
• Unused data/address pin can be used as general-purpose I/O ports.
• Capable of chip select output for completely independent four areas settable in 64 Kbytes minimum.
• Supports the following memory interfaces
SRAM, ROM/Flash
• Basic bus cycle: 2 cycles
• Programmable automatic wait cycle generation function capable of inserting wait cycles for each area
• RDY input for external wait cycles
•
Built-in memory
MB91V280
ROM/Flash
F-bus RAM
The peripheral circuits are described below.
See “■PRODUCT LINEUP” for the number of available channels on each model.
•
DMAC (DMA Controller)
• Capable of simultaneous operation of up to five channels
• Two forwarding factors (internal peripheral/software)
•
Bit search module (for REALOS)
Search for the position of the bit “1”/“0”-changed first in one word from the MSB
•
LIN UARTs (LIN-UART) : Up to 7 channels
• Asynchronous (start-stop synchronous) communications, clock synchronous communications
• Synch-Break detection
• Built-in baud rate generator on each channel
• Supports SPI (mode 2: Clock synchronous communication mode)
•
CAN CONTROLLERS : 3 channels (Max)
• High-speed transfer : 1 Mbps
• 32 message buffer (128 message buffer on the MB91V280)
(Continued)
2
External SRAM
48 Kbytes
MB91F272 (S)
Flash 256 Kbytes
10 Kbytes
MB91270/280 Series
•
Various timers
• 16-bit reload timer : 3 channels (including one channel for use by REALOS)
The internal clock can be divided by 2, 8, or 32
• 16-bit free-running timer: 4 channels
Output compare module: 8 channels
Input capture module: 8 channels
• 8/16-bit PPG timer: 8-bit x 16 channels or 16-bit x 8 channels
•
Interrupt controller
• Interrupt from internal peripheral
• Software-selectable priority level (16 levels)
•
D/A converter : 2 channels
8-bit or 10-bit resolution, R-2R type
•
A/D converter: 24 channels (MB91V280 has an additional module with eight more channels)
• 10-bit resolution
• Successive approximation conversion type
Conversion time : 3
µs
• Conversion mode (single conversion mode, continuous conversion mode)
• Activation source (software, external trigger, peripheral interrupt)
•
Other interval timer/counter
• 8/16-bit up down counter :
8 bits
×
4 channels or 16 bits
×
2 channels
• 16-bit timebase timer / watchdog timer
•
I
2
C bus interface* (400 Kbps): 3 channels
• Master/slave sending and receiving
• Arbitration and clock synchronization
•
Hardware watchdog
Interval time: 569 ms (Min), 771 ms (Max)
(Using a self-oscillation circuit (100 kHz) with a trimming function.)
•
I/O port
• Pull-up/pull-down can be controlled independently for each pin.
• The input level for each pin can be set to either CMOS Schmitt trigger levels or CMOS automotive Schmitt
trigger levels.
• The pin level can be read directly.
• Max 120 ports
•
Other features
• Internal oscillator circuit as clock source, allowing PLL multiplication to be selected
• INITX is prepared as a reset pin.
• Watchdog timer reset, software reset
• Available low-power consumption modes are stop mode, sleep mode, and real time clock mode.
Supports low-power consumption operation with CPU operating at 32 kHz (MB91F272 only).
• Gear function
• Built-in timebase timer
• Output clock (clock monitor)
(Continued)
3
MB91270/280 Series
(Continued)
• Clock Modulator
• Clock monitor function
Uses an internal self-oscillation circuit to monitor whether the main clock halts.
• Package
PGA-401, LQFP-100
• CMOS technology (0.35
µm)
• Power supply voltage: 3.5 V to 5.5 V
The 3.3 V supply to internal circuits is generated by an internal step-down circuit.
* : I
2
C license
Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined
by Philips.
4
MB91270/280 Series
■
PRODUCT LINEUP
Kind
Parameter
Package
Built - in ROM/Flash
RAM
External bus
External interrupt
DMAC (DMA Controller)
Clock modulator
Clock monitor function
Clock monitor
32 kHz sub-clock
Real time clock
CAN controllers
LIN UARTs (LIN-UART)
I
2
C interface
16 - bit reload timer
8/16-bit up down counter
16 - bit free - run timer
Input capture
Output compare
8/16-bit PPG
10-bit A/D converter
8/10-bit D/A converter
Pin pull-up/down
Input level selector
Debugging support
MB91F272 (S)
LQFP-100
Flash 256 Kbytes
10 Kbytes
Address : 24 bits
Data : 16 bits
(Multiplex only)
16 channels
5 channels
Yes
Yes
Yes
Option
(MB91F272 only)
Yes
1 channel (32 message buffer)
7 channels
3 channels
3 channels
2 channels
4 channels
8 channels
8 channels
16-bit x 8 channels
8-bit x 16 channels
24 channels
No
See “■PIN FUNCTION”
See “■PIN FUNCTION”
Wild register
MB91V280
PGA-401
External SRAM
48 Kbytes
Address : 24 bits
Data : 16 bits
40 channels
5 channels
Yes
Yes
Yes
Yes
Yes
3 channels (128 message buffer)
7 channels
3 channels
3 channels
2 channels
4 channels
8 channels
8 channels
16-bit x 8 channels
8-bit x 16 channels
24 channels + 8 channels
2 channels
All pins
All pins
DSU4
5
嵌入式系统
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