HD74LS74A
Dual D-type Positive Edge-triggered Flip-Flops
(with Preset and Clear)
REJ03D0415–0300
Rev.3.00
Jul.22.2005
Features
•
Ordering Information
Part Name
HD74LS74AP
HD74LS74AFPEL
HD74LS74ARPEL
Package Type
DILP-14 pin
SOP-14 pin (JEITA)
SOP-14 pin (JEDEC)
Package Code
(Previous Code)
PRDP0014AB-B
(DP-14AV)
PRSP0014DF-B
(FP-14DAV)
PRSP0014DE-A
(FP-14DNV)
Package
Abbreviation
P
FP
RP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
1CLR
1D
1CK
1PR
1Q
1Q
GND
1
2
3
4
5
6
7
CK
CLR PR
Q
Q
D
CK D
PR CLR
Q
Q
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CK
2PR
2Q
2Q
(Top view)
Rev.3.00, Jul.22.2005, page 1 of 7
HD74LS74A
Function Table
Input
Preset
L
H
L
H
H
Clear
H
L
L
H
H
Clock
X
X
X
↑
↑
D
X
X
X
H
L
Q
H
L
H*
H
L
Output
Q
L
H
H*
L
H
H
H
L
X
Q
0
Q
0
H; high level, L; low level, X; irrelevant,
↑;
transition from low to high level,
Q
0
; level of Q before the indicated steady-state input conditions were established.
Q
0
; complement of
Q
0
or level of Q before the indicated steady-state input conditions were established.
*;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
P
T
Tstg
Ratings
7
7
400
–65 to +150
Unit
V
V
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Pulse width
Setup time
Hold time
Clock High
Clear Preset
“H” Data
“L” Data
Symbol
V
CC
I
OH
I
OL
Topr
f
clock
t
w
t
w
t
su
t
su
t
h
Min
4.75
—
—
–20
0
25
25
20↑
20↑
5↑
Typ
5.00
—
—
25
—
—
—
—
—
—
Max
5.25
–400
8
75
25
—
—
—
—
—
Unit
V
µA
mA
°C
MHz
ns
ns
ns
Note:
↑;
The arrow indicates the rising edge.
Rev.3.00, Jul.22.2005, page 2 of 7
HD74LS74A
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
V
IH
V
IL
V
OH
Output voltage
V
OL
D
Clear
Preset
Clock
Input
current
D
Clear
Preset
Clock
D
Clear
Preset
Clock
Short-circuit output
current
Supply current
min.
2.0
—
2.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–20
—
typ.*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
max.
—
0.8
—
0.5
0.4
20
40
40
20
–0.4
–0.8
–0.8
–0.4
0.1
0.2
0.2
0.1
–100
8
Unit
V
V
V
V
V
CC
= 4.75 V, V
IH
= 2 V, V
IL
= 0.8 V,
I
OH
= –400
µA
I
OL
= 8 mA
I
OL
= 4 mA
V
CC
= 4.75 V, V
IL
= 0.8 V,
V
IH
= 2 V
Condition
I
IH
µA
V
CC
= 5.25 V, V
I
= 2.7 V
I
IL
mA
V
CC
= 5.25 V, V
I
= 0.4 V
I
I
mA
V
CC
= 5.25 V, V
I
= 7 V
I
OS
I
CC
**
mA
mA
V
CC
= 5.25 V
V
CC
= 5.25 V
Input clamp voltage
V
IR
—
—
–1.5
V
V
CC
= 4.75 V, I
IN
= –18 mA
Notes: * V
CC
= 5 V, Ta = 25
°
C
** With all output open, I
CC
is measured with the Q and
Q
outputs high in turn. At the time of measurement, the
clock input is grounded.
Switching Characteristics
(V
CC
= 5 V, Ta = 25°C)
Item
Maximum clock frequency
Propagation delay time
Symbol
f
max
t
PLH
t
PHL
Inputs
Clear, Clock
or Preset
Outputs
Q,
Q
min.
25
—
—
typ.
33
13
25
max.
25
40
Unit
MHz
ns
ns
Condition
C
L
= 15 pF,
R
L
= 2 kΩ
Timing Definition
t
w
3V
1.3 V
Clock
t
su
t
h
t
su
t
h
1.3 V
1.3 V
0V
3V
1.3 V
Data
"H" Data
"L" Data
1.3 V
1.3 V
0V
Rev.3.00, Jul.22.2005, page 3 of 7
HD74LS74A
Testing Method
Test Circuit
1.
ƒ
max
, t
PLH
, t
PHL
(Clock→Q,
Q)
4.5V V
CC
Input
R
L
P.G.
Z
out
= 50Ω
Input
P.G.
Z
out
= 50Ω
Output
Q
CK
CLR
Q
Same as Load Circuit 1.
PR
D
Q
C
L
Load circuit 1
Output Q
Notes:
1. Test is put into the each flip-flop.
2. C
L
includes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. t
PHL
, t
PLH
(Clear or Preset→ Q,
Q)
Input
P.G.
Z
out
= 50Ω
PR
D
Q
C
L
Output
Q
Input
P.G.
Z
out
= 50Ω
CK
CLR
Q
Same as Load Circuit 1.
R
L
Load circuit 1
V
CC
Output Q
Notes:
1. Test is put into the each flip-flop.
2. C
L
includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Rev.3.00, Jul.22.2005, page 4 of 7
HD74LS74A
Waveforms 1
t
TLH
t
THL
t
w
(L)
1.3 V
10%
t
w
(H)
0V
3V
3V
90% 90%
1.3 V 1.3 V
Clock
10%
D
t
PLH
1.3 V
Q
t
PHL
t
PLH
t
PHL
0V
V
OH
1.3 V
V
OL
Q
1.3 V
1.3 V
V
OH
V
OL
Note:
Clock input pulse; t
TLH
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz, duty cycle = 50% and for f
max
,
t
TLH
= t
THL
≤
2.5 ns
Waveforms 2
t
THL
Clear
90%
1.3V
10%
t
w (clear)
≥
25ns
Preset
t
TLH
90%
1.3V
10%
t
THL
90%
1.3V
10%
t
w (preset)
t
PHL
≥
25ns
t
PLH
Q
t
PLH
1.3V
1.3V
V
OL
V
OH
Q
1.3V
t
PHL
1.3V
V
OL
V
OH
t
TLH
90%
1.3V
10%
3V
0V
3V
0V
Note:
Crear and presel input pulse; t
TLH
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz,
Rev.3.00, Jul.22.2005, page 5 of 7
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
