GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
333 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Functional Description
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m
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
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Paramter Synopsis
-333
2.5
3.0
250
290
4.5
4.5
200
230
d
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
is implemented with GSI's high performance CMOS
technology and is available in a JEDEC-standard 100-pin
TQFP package.
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-300
2.5
3.3
230
265
5.0
5.0
185
210
N
-250
2.5
4.0
200
230
5.5
5.5
160
185
ew
-200
3.0
5.0
170
195
6.5
6.5
140
160
D
3.8
6.7
140
160
7.5
7.5
128
145
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
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ot
R
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
N
Flow Through
2-1-1-1
Rev: 1.06a 2/2008
1/39
es
-150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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n
Unit
ns
ns
mA
mA
ns
ns
mA
mA
© 2002, GSI Technology
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A
DQ
B
DQ
C
DQ
D
DQP
A
DQP
B
DQP
C
DQP
D
ZZ
FT
LBO
V
DD
V
SS
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
In
In
In
In
In
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A
; active low
Byte Write signal for data inputs DQ
C
; active low
Byte Write signal for data inputs DQ
D
; active low
Chip Enable; active low
Write Enable; active low
Chip Enable—Active Low. For self decoded depth expansion
Advance/Load; Burst address counter control pin
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d
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R
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
Core power supply
Ground
Output driver power supply
V
DDQ
Rev: 1.06a 2/2008
N
5/39
fo
r
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
9th Data I/O Pin; Byte A
9th Data I/O Pin; Byte B
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
Power down control; active high
N
Output Enable; active low
ew
Chip Enable—Active High. For self decoded depth expansion
D
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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n
Byte Write signal for data inputs DQ
B
; active low
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