Features
•
Up to 128-voice Top-quality Wavetable Synthesis Chip
– Two 64-voice RISC DSP Cores
– Two High-speed CISC Control Processor
– Versatile Programmable Digital Audio Routing Between the Two DSPs
Voices Can Be Allocated for Synthesis and/or Effects and/or Audio Processing
Maximum Single-shot PCM Wavesize of 4M Samples (93 Seconds @ 44.1 kHz)
Samples Can Be Stored in 16-bit Floating Point Format (20-bit Dynamic), 16-bit Linear,
8-bit Linear
Standard Audio Processing Firmware Includes Equalizer, Surround, MPEG Audio
Decoder (Level 2)
Sophisticated Built-in Cache Memories
– Allows Use of Standard 100 ns 16-bit ROMs/RAMs
– Guarantees Crisp Response Even Under Heavy Traffic Conditions
GS
®
Sound Set
(1)
under License from Roland
®
Corporation, Other Sound Sets Available
16-channel Audio-in, 16-channel Audio-out @ 22 Bits Audio/Channel
28-bit Internal Audio Path
Two Serial MIDI-In, Two Serial MIDI-Out
Firmware/Wavetable Data Can Reside in ROM, DRAM, SDRAM
Up to 256M Bytes of External Memory with Support of SIMM (DRAM) and DIMM
(SDRAM)
High-speed 16-bit Burst Transfer for Firmware Download or Streaming Audio
Compatible with SAM9707, Uses Proven Design and Development Tools
– Sound Editor, Sound Bank Editor
– Algorithm Compiler, Assembler, Source Debugger
– Direct Development from PC Environment, No Special Emulator Required
Top Technology
– Single Low-frequency Crystal and Built-in PLL
– 3.3V Supply, 5V-tolerant I/Os
– Space-saving 144-lead TQFP Package
– Power-down Mode
Typical Applications: Karaokes, High-range Multimedia, Classical Organs, Digital
Pianos, Professional Keyboards, Musical Samplers
1. The GS Sound Set is subject to special licensing conditions. Not to be used for
musical instruments.
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128-voice
Integrated
Sound
Synthesizer
SAM9708
•
•
Note:
Description
The SAM9708 is a 128-voice integrated synthesizer, integrating two PDSP blocks and
a memory management unit (MMU). One PDSP block is a combination of a special-
ized 64-slot RISC-based digital signal processor (DSP), a general-purpose 16-bit
CISC-based control processor (P16), a cache memory and an “intelligent” peripheral
I/O interface. Both PDSPs are fully independent and share the same external memory
through the MMU.
Rev. 1772B–01/02
1
Block Diagrams
Figure 1.
SAM9708 Block Diagram
16-bit Bus
PDSP 1
MIDI and Audio
MMU
Memory
PDSP 2
Figure 2.
PDSP Block Diagram
I/O Functions
16-bit Bus
MIDI
Control/Status
MIDI UART
Timers
Host I/F
P16 Processor
16-bit CISC
Processor Core
Includes
256 x 16 Data RAM
256 x 16 Boot ROM
MMU
Synthesis/DSP
RISC DSP Core
Includes
512 x 38 Alg RAM
128 x 28 MA1 RAM
256 x 32 MA2 RAM
256 x 32 MB RAM
128 x 16 MX RAM
256 x 16 MY RAM
64 x 13 ML RAM
Audio
Cache Memory
128 x 16
2
SAM9708
1772B–01/02
SAM9708
Pin Description by Function
Table 1.
Power Group
Name
GND
VC3
VCC1
VCC2
Pin Count
19
8
5
5
Type
PWR
PWR
PWR
PWR
Function
Power Ground. All GND pins should be returned to digital ground.
Core Power, +3.3V nominal (3V to 4.5V). All V
C3
pins should be returned to
+3.3V.
Pad (except Memory Pad) Power, +3.0V to +5.5V. All V
CC
pins should be
returned to +5V (or 3.3V in case of single 3.3V supply).
Memory Pad Power, +3.0V to +5.5V. All V
CC
pins should be returned to +5V (for
RAM or DRAM) or 3.3V (for SDRAM or 3.3V ROM).
Table 2.
ISA Bus Group
(1)
Name
PC_D[15:0]
(2, 3)
Pin Count
16
Type
I/O
Function
16-bit data bus to host processor.
Information on these pins is:
- 2 x parallel MIDI (MPU-401 type applications)
- 2 x high-speed burst data transfers to/from external memory
Selects one of 8 internal registers:
0, 1: MPU-401 register processor #1
2, 3: Burst data (16-bit) processor #1
4 - 5: MPU-401 register processor #2
6 - 7: Burst data (16-bit) processor #2
Chip select from host, active low.
Write from host, active low.
Read from host, active low.
Open drain output buffer. Driven low during 16-bit burst mode transfers to
synchronize host to the SAM9708 memory.
Open drain output buffer; driven low during 16-bit burst mode transfers.
Indicates to host that a 16-bit I/O is in progress.
Tri-state output pin, active high. Can be connected directly to host IRQ line.
PC_A[2:0]
3
IN
PC_CS
PC_WR
PC_RD
PC_READY
PC_IO16
PC_IRQ
Notes:
1
1
1
1
1
1
IN
IN
IN
TSout
TSout
TSout
1. ISA bus group pins are powered by V
CC1
power rail.
2. PC_D pads have 4 mA drive capabilities; other output pads have 16 mA drive capabilities.
3. To interface with PC ISA bus, V
CC1
should be connected to 5V power and PC_D bus should be buffered. Direction is given by
PC_RD signal.
3
1772B–01/02
Table 3.
MIDI and Audio Group
(1)
Name
MIDI1_IN
MIDI2_IN
MIDI1_OUT
MIDI2_OUT
OVCK_OUT
BCK_OUT
WS_OUT
SD_OUT[7:0]
SD_IN[7:0]
Pin Count
1
1
1
1
1
1
1
8
8
Type
IN
I/O
OUT
OUT
OUT
OUT
OUT
OUT
I/O
Function
Main MIDI input. Routed to PDSP#1, can also be routed to PDSP#2.
Auxiliary MIDI input. Routed to PDSP#2
(2)
Main MIDI output. Outputs from PDSP#1.
Auxiliary MIDI output. Outputs from PDSP#2
(2)
Buffered X2 output. Typically used to drive external sigma/delta DAC/ADC at
f
S
x 256.
Audio data bit clock. Provides timing to SD_OUT.
Audio data word select. WS_OUT timing can be selected to be I2S- or
Japanese-compatible.
8 stereo serial audio data output (16 audio channels). Each output holds 64 bits
(2 x 32) of serial data per frame. Audio data has 22-bit precision
(2)
.
8 stereo serial audio data input (16 audio channels). Each input holds 64 bits
(2 x 32) of serial data per frame. Audio data in is received with 20-bit
precision
(2)
.
Notes:
1. MIDI and Audio group pins are powered by V
CC1
power rail.
2. These pins have alternate functions as GPIO pins (general-purpose input/output pins). See “General-purpose Input/Output
Routing” on page 23 for more details.
Table 4.
Memory Group
(1)
Name
CK_OUT
WA[26:0]
Pin Count
1
27
Type
OUT
OUT
Function
Master clock for SDRAM operation. Frequency is 4 times the X1 frequency
(typ 45.1584 MHz).
External memory address (ROM/SRAM/DRAM/SDRAM), up to 128M words
(256M bytes).
DRAM/SDRAM addresses are time-multiplexed on these pins as follows:
WA0 - WA8: DRA0 - DRA8
WA18: DRA9
WA20: DRA10
WA22: DRA11
SRAM byte select. Should be connected to the lower RAM address when 8-bit
wide SRAM is used. The type of RAM (16-bit/8-bit) can be selected by
program.
PCM ROM/SRAM/DRAM/SDRAM data
PCM ROM chip select, active low
SRAM chip select, active low
SRAM/DRAM/SDRAM write enable, active low. Timing compatible with SIMM
DRAM early write feature.
PCM ROM/SRAM output enable, active low
RBS
1
OUT
WD[15:0]
WCS0
WCS1
WWE
WOE
16
1
1
1
1
I/O
OUT
OUT
OUT
OUT
4
SAM9708
1772B–01/02
SAM9708
Table 4.
Memory Group
(1)
(Continued)
Name
RAS
Pin Count
1
Type
I/O
Function
DRAM/SDRAM row address strobe. At the end of reset RAS is tested to
determine memory type configuration (pulled high to select SDRAM type). RAS
should be pulled to V
CC
or GND through an external 10K resistor.
DRAM/SDRAM column address strobe. At the end of reset CAS is tested to
determine memory type configuration (pulled high to select DRAM type). CAS
should be pulled to V
CC
or GND through an external 10K resistor.
Indicates that a DRAM/SDRAM memory refresh cycle is in progress. To be
used with multiple SIMM/DIMM modules to force refresh simultaneously on all
modules. At the end of reset REFRESH is tested to select bootstrap state
(pulled high to start built-in CPU bootstrap in case of ROMless applications).
CAS
1
I/O
REFRESH
1
I/O
Note:
1. Memory group pins are powered by V
CC2
power rail.
Table 5.
Miscellaneous Group
Name
LFT
TEST
LDTEST
PDWN
RESET
X1, X2
Pin Count
1
1
1
1
1
2
Type
ANA
IN
IN
IN
IN
–
Function
PLL low pass filter. Should be connected to an external RC network.
Test pin. Should be returned to GND.
Test pin. Should be returned to GND.
Power down, active low
Master reset input, active low. Schmidt trigger input.
Crystal connection. Crystal frequency should be f
S
x 256 (typ 11.2896 MHz).
Crystal frequency is internally multiplied by 4 to provide the IC master clock. X1
can also be used as external clock input (3.3V input).
X2 CANNOT BE USED TO DRIVE EXTERNAL CIRCUITRY
5
1772B–01/02
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