®
HIGH-PERFORMANCE
CMOS BUFFERS
Integrated Device Technology, Inc.
IDT54/74FCT827A
IDT54/74FCT827B
IDT54/74FCT827C
FEATURES:
• Faster than AMD’s Am29827 series
• Equivalent to AMD’s Am29827 bipolar buffers in pinout/
function, speed and output drive over full temperature
and voltage supply extremes
• IDT54/74FCT827A equivalent to FAST™
• IDT54/74FCT827B 35% faster than FAST
• IDT54/74FCT827C 45% faster than FAST
• I
OL
= 48mA (commercial), and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT827A/B/C 10-bit bus drivers provide
high-performance bus interface buffering for wide data/ ad-
dress paths or buses carrying parity. The 10-bit buffers have
NAND-ed output enables for maximum control flexibility.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
OE
1
OE
2
2609 drw 01
PRODUCT SELECTOR GUIDE
10-Bit Buffer
Non-inverting
IDT54/74FCT827A/B/C
2609 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4612/2
7.20
1
IDT54/74FCT827A/B/C
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4 P24-1
5 D24-1
6 E24-1
&
7
8 SO24-2
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
OE
2
D
1
D
0
OE
1
NC
V
CC
Y
0
Y
1
LOGIC SYMBOL
INDEX
D
2
D
3
D
4
NC
D
5
D
6
D
7
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
D
8
D
9
GND
NC
OE
2
Y
9
Y
8
4 3 2
D
0-9
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
10
10
Y
0-9
OE
1
OE
2
2609 drw 04
2609 drw 02
2609 drw 03
DIP/CERPACK/SOIC
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
Name
I/O
FUNCTION TABLE
(1)
Inputs
Output
D
I
L
H
X
X
Y
I
L
H
Z
Z
Function
Transparent
Three-State
2609 tbl 03
OE
I
D
I
Y
I
I
I
O
Description
When both are LOW, the outputs are
enabled. When either one or both are
HIGH, the outputs are High Z.
10-bit data input.
10-bit data output.
2609 tbl 02
OE
1
L
L
H
X
OE
2
L
L
X
H
NOTE:
1. H = HIGH, L = LOW, X = Don’t Care, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
(3)
Terminal Voltage
V
TERM
–0.5 to V
CC
with Respect to
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
–0.5 to V
CC
V
°C
°C
°C
W
mA
–55 to +125
–65 to +135
–65 to +150
0.5
120
NOTE:
2609 tbl 05
1. This parameter is measured at characterization but not tested.
NOTES:
2609 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability. No terminal voltage may
exceed V
CC
by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.20
2
IDT54/74FCT827A/B/C
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
OH
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Off State (High Impedance)
Output Current
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
CC
= Max.
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–75
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
Unit
V
V
µ
A
µ
A
V
mA
V
I
OH
= –300
µ
A
I
OH
= –15mA MIL.
I
OH
= –24mA COM'L.
V
OL
Output LOW Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 300
µ
A
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
2609 tbl 06
7.20
3
IDT54/74FCT827A/B/C
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
1
=
OE
2
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
Eight Bits Toggling
Min.
—
—
V
IN
≥
V
HC
V
IN
≤
V
LC
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4.0
mA
—
2.0
5.0
—
3.2
6.5
(5)
—
5.2
14.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2609 tbl 07
7.20
4
IDT54/74FCT827A/B/C
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT827A
Com'l.
Parameter
Description
Conditions
(1)
Mil.
IDT54/74FCT827B
Com'l.
Mil.
IDT54/74FCT827C
Com'l.
Mil.
Unit
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
t
PLH
t
PHL
Propagation Delay
D
I
to Y
I
C
L
= 50pF
R
L
= 500
Ω
C
L
= 300pF
(3)
R
L
= 500
Ω
C
L
= 50pF
R
L
= 500
Ω
C
L
= 300pF
(3)
R
L
= 500
Ω
C
L
= 5pF
(3)
R
L
= 500
Ω
C
L
= 50pF
R
L
= 500
Ω
1.5
8.0
1.5
9.0
1.5
5.0
1.5
6.5
1.5
4.4
1.5
5.0
ns
1.5 15.0
1.5 12.0
1.5 23.0
1.5
9.0
1.5 17.0
1.5 13.0
1.5 25.0
1.5
9.0
1.5 13.0
1.5
8.0
1.5 14.0
1.5
9.0
1.5 10.0
1.5
7.0
1.5 11.0
1.5
8.0
ns
t
PZH
t
PZL
Output Enable Time
OE
I
to Y
I
1.5 15.0
1.5
1.5
6.0
7.0
1.5 16.0
1.5
1.5
7.0
8.0
1.5 14.0
1.5
1.5
5.7
6.0
1.5 15.0
1.5
1.5
6.7
7.0
2609 tbl 08
t
PHZ
t
PLZ
Output Disable Time
OE
I
to Y
I
ns
1.5 10.0
1.5 10.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
7.20
5
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