IDT74FCT823AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTER
IDT74FCT823AT/BT/CT/DT
FEATURES:
−
−
−
−
−
−
−
−
Low input and output leakage
≤1µ
A (max.)
CMOS power levels
True TTL input and output compatibility
•
V
OH
= 3.3V (typ.)
•
V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Available in SOIC, SSOP, and QSOP packages
A, B, C and D speed grades
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit “live insertion”
DESCRIPTION:
The FCT823T series is built using an advanced dual metal CMOS
technology. The FCT823T series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The FCT823T are 9-bit wide buffered registers with Clock Enable
(EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance
microprogrammed systems.
The FCT823T high-performance interface family can drive large capaci-
tive loads, while providing low-capacitance bus loading at both inputs and
outputs. All inputs have clamp diodes and all outputs are designed for low-
capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
EN
D
N
CLR
D
CL
Q
D
CL
Q
CP
Q
CP
Q
CP
OE
Y
0
Y
N
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
AUGUST 2000
DSC-5487/-
IDT74FCT823AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
C LR
GN D
1
2
3
4
5
6
7
8
9
10
11
12
SO24-2
SO24-7
SO24-8
ABSOLUTE MAXIMUM RATINGS
(1)
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Rating
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
8T-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8T-link
SOIC/ SSOP/ QSOP
TOP VIEW
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Names
D
I
CLR
I/O
I
I
Description
The D flip-flop data inputs.
When the clear input is LOW and
OE
is LOW,
the Q
I
outputs are LOW. When the clear input is
HIGH, data can be entered into the register.
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
The register 3-state outputs.
Clock Enable. When the clock enable is LOW,
data on the D
I
input is transferred to the Q
I
output on the LOW-to-HIGH clock transition.
When the clock enable is HIGH, the Q
I
outputs
do not change state, regardless of the data or
clock input transitions.
Output Control. When the
OE
input is HIGH, the
Y
I
outputs are in the high-impedance state.
When the
OE
input is LOW, the TRUE register
data is present at the Y
I
outputs.
FUNCTION TABLE
Inputs
OE
H
H
H
L
H
L
H
H
L
L
CLR
H
H
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
D
I
L
H
X
X
X
X
L
H
L
H
(1)
Internal/
Outputs
Q
I
Y
I
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
NC
Z
Z
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Function
High Z
Clear
Hold
Load
CP
Y
I
EN
I
O
I
OE
I
NOTE:
1. H = HIGH
L = LOW
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
Z = High-Impedance
2
IDT74FCT823AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output Pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
Unit
V
V
µA
µA
µA
V
mV
mA
V
CC
= Max., V
IN
=
GND or
V
CC
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
V
OL
I
OS
I
OFF
Parameter
Output HIGH Voltage
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
=
V
IH
or V
IL
V
CC
= Min.
V
IN
=
V
IH
or V
IL
V
CC
= Max., V
O
= GND
(3)
V
CC
= 0V, V
IN
or V
O
≤
4.5V
–60
—
–120
—
–225
±1
mA
µA
Test Conditions
(1)
I
OH
= –8mA
I
OH
= –15mA
I
OL
= 48mA
Min.
2.4
2
—
Typ.
(2)
3.3
3
0.3
Max.
—
—
0.5
V
Unit
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
3
IDT74FCT823AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
=
EN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
6
16.3
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT74FCT823AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT823AT
Symbol
Parameter
t
PLH
Propagation Delay
CP to Y
I
(OE = LOW)
t
PHL
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
Min
.
(2)
1.5
1.5
4
2
4
2
1.5
6
7
6
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 5pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
1.5
1.5
1.5
1.5
Max.
10
20
—
—
—
—
14
—
—
—
12
23
7
8
FCT823BT
Min
.
(2)
1.5
1.5
3
1.5
3
0
1.5
6
6
6
1.5
1.5
1.5
1.5
Max.
7.5
15
—
—
—
—
9
—
—
—
8
15
6.5
7.5
FCT823CT
Min
.
(2)
1.5
1.5
3
1.5
3
0
1.5
6
6
6
1.5
1.5
1.5
1.5
Max.
6
12.5
—
—
—
—
8
—
—
—
7
12.5
6
6.5
FCT823DT
Min
.
(2)
1.5
1.5
2
1
3
0
1.5
3
3
3
1.5
1.5
1.5
1.5
Max.
5
8.5
—
—
—
—
5
—
—
—
4.8
9
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
t
SU
t
H
t
SU
t
H
t
PHL
t
REM
t
W
t
W
t
PZH
t
PZL
Set-up Time HIGH or LOW D
I
to CP
Hold Time HIGH or LOW D
I
to CP
Set-up Time HIGH or LOW
EN
to CP
Hold Time HIGH or LOW
EN
to CP
Propagation Delay,
CLR
to Y
I
Recovery Time
CLR
to CP
Clock Pulse Width HIGH or LOW
CLR
Pulse Width LOW
Output Enable Time
OE
to Y
I
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
5
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