AN-794
Using an EEPROM—
IIC
Interface
NM24C02/03/04/05/08/09/
16/17
INTRODUCTION
Fairchild Semiconductor’s NM24C EEPROMs are designed to
interface with Inter-Integrated Circuit (IIC) buses and hardware.
Fairchild’s electrically erasable programmable read only memo-
ries (EEPROMs) offer valuable security features (write protec-
tion), two write modes, three read modes and a wide variety of
memory sizes. Applications for the IIC bus and NM24C memories
are included in SANs (small-area networks), stereos, televisions,
automobiles and other scaled-down systems that don’t require
tremendous speeds but instead cost efficiency and design sim-
plicity.
Fairchild
Application Note 794
ration used by the IIC interface compared to that of the
MICROWIRE™ and SPI interface, reduced board space and pin
count allows the designer to have more creative flexibility while
reducing interconnecting cost.
OPERATING Fairchild SEMICONDUCTOR’S
NM24Cs
The NM24C E
2
PROMs require only six simple operating codes for
transmitting or receiving bits of information over the 2-wire IIC bus.
These fields are explained in greater detail below and briefly
described hereafter: a start bit, a 7-bit slave address, a read/write
bit which defines whether the slave is a transmitter or receiver, an
acknowledge bit, message bits divided into 8-bit segments and a
stop bit.
For efficient and faster serial communication between devices,
the NM24C Family features page write and sequential read.
The NM24C03/C05/C09/C16/C17 Family offers a security feature
in addition to standard features found in the NM24C02/C04/C08/
C16 Family. The security feature is beneficial in that it allows Read
Only Memory (ROM) to be implemented in the upper half of the
memory to prevent any future programming in that particular chip
section; the remaining memory that has not been write protected
can still be programmed. The security feature in the NM24C03/
C05/C09/C17 Family does not require immediate implementation
when the device is interfaced to the IIC bus, which gives the
designer the option to choose this feature at a later date. Table 1
displays the following parameters: memory content, write protect
and the maximum number of individual IIC E
2
PROMs allowed on
an IIC bus at one time if the total line capacitance is kept below 400
pF.
Code used to interface the NM24Cs with Fairchild Semiconductor’s
COP8™ Microcontroller Family is listed in a latter section of this
application note for further information to the reader.
IIC
BACKGROUND
The IIC bus configuration is an amalgam of microcontrollers and
peripheral controllers. By definition: a device that transmits sig-
nals onto the IIC bus is the “transmitter” and a device that receives
signals is the “receiver”; a device that controls signal transfers on
the line in addition to controlling the clock frequency is the “master”
and a device that is controlled by the master is the “slave”. The
master can transmit or receive signals to or from a slave, respec-
tively, or control signal transfers between two slaves, where one
is the transmitter and the other is the receiver. It is possible to
combine several masters, in addition to several slaves, onto an IIC
bus to form a multimaster system. If more than one master
simultaneously tries to control the line, an arbitration procedure
decides which master gets priority. The maximum number of
devices connected to the bus is dictated by the maximum allow-
able capacitance on the lines, 400 pF, and the protocol’s address-
ing limit of 16k; typical device capacitance is 10 pF. Up to eight
E
2
PROMs can be connected to an IIC bus, depending on the size
of the memory device implemented.
Simplicity of the IIC system is primarily due to the bidirectional 2-
wire design, a serial data line (SDA) and serial clock line (SKL),
and to the protocol format. Because of the efficient 2-wire configu-
TABLE 1.
Part No.
NM24C02
NM24C03
NM24C04
NM24C05
NM24C08
NM24C09
NM24C16
NM24C17
Number of
256x8 Page Blocks
1
1
2
2
4
4
8
8
Write Protect
Feature
No
Yes
No
Yes
No
Yes
No
Yes
Max.
Parts
8
8
4
4
2
2
1
1
© 1998 Fairchild Semiconductor Corporation
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AN-794
Master 1
Data
Slave 1
(RAM)
Clock
Slave 2
(EEPROM)
Master 2
FIGURE 1.
IIC-Bus
Configurations
Slave address
Clock
Data
B1
1
B2
1
. . . . . . . . B8
1
ACK
t
HS
B8
n
ACK
t
HP
t
BF
FIGURE 2.
IIC
Bus Timing
Start Condition
— Clock and Data line high (Bus free)
— Change Data line from high to low
— After t
HS(Min)
= 4
µs
the master supplies the clock
Acknowledge
— Transmitting device releases the Data line
— The receiving device pulls the Data line low during the ACK-clock if there is no error
— If there is no ACK, the master will generate a Stop Condition to abort the transfer
Stop Condition
— Clock line goes high
— After t
HP(Min)
= 4.7
µs
the Data lines go high
— The master maintains the Data and Clock line high
— Next Start Condition after t
FB(Min)
= 4.7
µs
is possible
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AN-794
START/STOP CONDITIONS
If both the data and clock lines are HIGH, the bus is not busy. To
attain control of the bus, a start condition is needed from a master;
and to release the lines, a stop condition is required.
Start Condition: HIGH-to-LOW transition of the data line while
the clock line is in a HIGH state.
Stop Condition: LOW-to-HIGH transition of the data line while
the clock line is in a HIGH state.
The master always generates the start and stop conditions. After
the start condition the bus is in the busy state. The bus becomes
free after the stop condition.
ARBITRATION
Only in multimaster systems.
If more than one device are potential masters and more than one
desires access to the bus, an arbitration procedure takes place: if
a master transmits a HIGH level and another master transmits a
LOW level, the master with the LOW level will get the bus and the
other master will release the bus; and the clock line switches
immediately to the slave receiver mode. This arbitration could
carry on through many bits (address bits and data bits are used for
arbitration).
FORMATS
There are three data transfer formats supported:
— Master transmitter writes to slave receiver; no direction
change
— Master reads immediately after sending the address byte
— Combined format with multiple read or write tranfers.
DATA BIT TRANSFER
After a start condition “S” one databit is transferred during each
clock pulse. The data must be stable during the HIGH-period of the
clock. The data line can only change when the clock line is at a
LOW level.
Normally each data transfer is done with 8 data bits and 1
acknowledge bit (byte format with acknowledge).
ADDRESSING
The 7-bit address of an IIC device and the direction of the following
data is coded in the first byte after the start condition:
MSB
MSB
R/W
Slave Address
ACKNOWLEDGE
Each data transfer needs to be acknowledged. The master
generates the acknowledge clock pulse. The transmitter releases
the data line (SDA = HIGH) during the acknowledge clock pulse.
If there was no error detected, the receiver will pull down the SDA-
line during the HIGH period of the acknowledge clock pulse.
If a slave receiver is not able to acknowledge, the slave will keep
the SDA line HIGH and the master can then generate a STOP
condition to abort the transfer.
If a master receiver keeps the SDA line HIGH, during the acknowl-
edge clock pulse the master signals the end of data transmission
and the slave transmitter release the data line to allow the master
to generate a STOP-condition.
A “0” on the least significant bit indicates that the master will write
information to the selected Slave address device; a “1” indicates
that the master will read data from the slave.
Some slave addresses are reserved for future use. These are all
addresses with the bit combinations 1111XXX and 0000XXX. The
address 00000000 is used for a general call address, for example,
to initialize all I
2
C devices (refer to I
2
C bus specification for detailed
information).
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AN-794
Master Transmits to Slave, No Direction Change
S Slave Address R W A
"0" = WRITE
Data
A
Data
A
P
Data transferred
(in bytes + Acknowledge)
Master Reads Slave Immediately after First Byte
S
Slave Address R W A
"1" READ
Data
A
Data
A
P
Data transferred
(in bytes + Acknowledge)
The master becomes a master receiver after first ACK
Combined Formats
S
Slave Address R W A
Read or Write
n bytes Data + ACK
n bytes Data + ACK
S = Start Condition
A = Acknowledge
P = Stop Condition
Data
A
S
Slave Address
R W
A
Read or Write
Data
A
P
FIGURE 3. IIC-Bus Transfer Formats
TIMING
The master can generate a maximum clock frequency of 100 KHz.
The minimum LOW period is defined as 4.7
µs;
the minimum HIGH
period width is 4
µs;
the maximum rise time on SDA and SCL is 1
µs;
and the maximum fall time on SDA and SCL is 300 ns. Figure
4 shows the detailed timing requirements.
Symbol
f
SCL
t
BUF
t
HD:STA
t
LOW
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
Parameter
SCL Clock Frequency
Time the Bus Must Be Free before a New Transmission
Can Start
Hold Time Start Condition. After this Period the First Clock
Pulse is Generated
The LOW Period of the Clock
Setup Time for Start Condition
(Only Relevant for a Repeated Start Condition)
Data in Hold Time
Setup Time Data
Rise Time of Both SDA and SCL Lines
Fall time of Both SDA and SCL Lines
Setup Time for Stop Condition
Min
0
4.7
4.0
4.7
4.7
5
0 (Note 1)
250
Max
100
Units
kHz
µs
µs
µs
µs
µs
µs
ns
1
300
4.7
µs
ns
µs
Note 1:
Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL.
FIGURE 4.
IIC-Bus
Timing Requirements
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AN-794
+
+
+
4
3
COP820C
28-PIN
5
6
NM24C02
2k BIT
A0
1
A1
2
+5V
A2
3
8
V
DD
39k
7
4
23
FIGURE 5.
IIC
Bus EEPROM/
µ
Controller Configuration Used for Sam ple Code
SOFTWARE TASKS
I. Write fixed values to E
2
PROM cells
II. Read values back from E
2
PROM and save in RAM locations
from COP
Note:
IIC Bus Modes Used:
REMARKS
— The IIC bus, 2-wire serial interface generally requires a pull-
up resistor on the SDA line and the SCL line, depending on
whether TTL or CMOS hardware interfacing exists.
— I IC bus compatible
µC’s
or peripherals have OPEN DRAIN
outputs at SDA and SCL.
— COP800 does not have OPEN DRAIN outputs, but the “bus
requirements” can be met by switching SDA and SCL
connections into TRI-STATE
®
for the following cases:
The bus is not accessed
A slave has to send an acknowledge bit.
— MICROWIRE can not be used for I
2
C bus operations.
— Current sink capability on SDA and SCL must be 3 mA to
maintain “Low Level” (an IIC bus spec.).
Master
Transmitter
Master Receiver
SDA
¡
SCL
¡
¡
SDA
Slave Receiver
Slave Receiver
SCL
¡
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