CAT28LV65
64 kb CMOS Parallel
EEPROM
Description
The CAT28LV65 is a low voltage, low power, CMOS Parallel
EEPROM organized as 8K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and V
CC
power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling, RDY/BUSY and Toggle status bit signal the start and end of
the self−timed write cycle. Additionally, the CAT28LV65 features
hardware and software write protection.
The CAT28LV65 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP,
28−pin SOIC or 32−pin PLCC packages.
Features
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PDIP−28
P, L SUFFIX
CASE 646AE
SOIC−28
J, K, W, X SUFFIX
CASE 751BM
•
3.0 V to 3.6 V Supply
•
Read Access Times:
•
•
•
•
•
•
•
•
•
•
•
– 150/200/250 ns
Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100
mA
Max.
Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
Fast Write Cycle Time:
– 5 ms Max.
Commercial, Industrial and Automotive Temperature Ranges
CMOS and TTL Compatible I/O
Automatic Page Write Operation:
– 1 to 32 bytes in 5 ms
– Page Load Timer
End of Write Detection:
– Toggle Bit
– DATA Polling
– RDY/BUSY
Hardware and Software Write Protection
100,000 Program/Erase Cycles
100 Year Data Retention
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PLCC−32
N, G SUFFIX
CASE 776AK
TSOP−28
H13 SUFFIX
CASE 318AE
PIN FUNCTION
Pin Name
A
0
−A
12
I/O
0
−I/O
7
CE
OE
RDY/BSY
WE
V
CC
V
SS
NC
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Ready/BUSY Status
Write Enable
3.0 V to 3.6 V Supply
Ground
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 7
1
Publication Order Number:
CAT28LV65/D
CAT28LV65
PIN CONFIGURATIONS
DIP Package (P, L)
RDY/BUSY
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
SOIC Package (J, K, W, X)
RDY/BUSY
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
PLCC Package (N, G)
A
7
A
12
RDY/BUSY
NC
V
CC
WE
NC
TSOP Package (8 mm x 13.4 mm) (H13)
OE
A
11
A
9
A
8
NC
WE
V
CC
RDY/BUSY
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
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2
CAT28LV65
A
5
−A
12
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
V
CC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
DATA POLLING
RDY/BUSY &
TOGGLE BIT
COLUMN
DECODER
I/O BUFFERS
TIMER
ADDR. BUFFER
& LATCHES
I/O
0
−I/O
7
A
0
−A
4
RDY/BUSY
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
–2.0 V to +V
CC
+ 2.0 V
−2.0
to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
(Note 3)
Symbol
N
END
T
DR
V
ZAP
I
LTH
(Note 4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
10
5
100
2,000
100
Max
Units
Cycles/Byte
Years
V
mA
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+ 1 V.
Table 3. MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High−Z
High−Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
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CAT28LV65
Table 4. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz)
Symbol
C
I/O
(Note 5)
C
IN
(Note 5)
Test
Input/Output Capacitance
Input Capacitance
Max
10
6
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Units
pF
pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
Table 5. D.C. OPERATING CHARACTERISTICS
(V
CC
= 3.0 V to 3.6 V, unless otherwise specified.)
Limits
Symbol
I
CC
I
SBC
(Note 6)
I
LI
I
LO
V
IH
(Note 6)
V
IL
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
I
OH
=
−100
mA
I
OL
= 1.0 mA
2
Test Conditions
CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
CE = V
IHC
, All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE = V
IH
−1
−5
2
−0.3
2
0.3
Min
Typ
Max
8
100
1
5
V
CC
+ 0.3
0.6
Units
mA
mA
mA
mA
V
V
V
V
V
6. V
IHC
= V
CC
−
0.3 V to V
CC
+ 0.3 V.
Table 6. A.C. CHARACTERISTICS, READ CYCLE
(V
CC
= 3.0 V to 3.6 V, unless otherwise specified.)
28LV65−15
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ
(Note 7)
t
OLZ
(Note 7)
t
HZ
(Notes 7, 8)
t
OHZ
(Notes 7, 8)
t
OH
(Note 7)
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High−Z Output
OE High to High−Z Output
Output Hold from Address
Change
0
0
0
50
50
0
Min
150
150
150
70
0
0
50
50
0
Max
28LV65−20
Min
200
200
200
80
0
0
55
55
Max
28LV65−25
Min
250
250
250
100
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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4
CAT28LV65
V
CC
−
0.3 V
INPUT PULSE LEVELS
0.0 V
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform
(Note 9)
9. Input rise and fall times (10% and 90%) < 10 ns.
V
CC
1.8 K
DEVICE
UNDER
TEST
1. 3 K
C
L
= 100 pF
OUTPUT
C
L
INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE
(V
CC
= 3.0 V to 3.6 V, unless otherwise specified.)
28LV65−15
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
(Note 10)
t
OES
t
OEH
t
WP
(Note 10)
t
DS
t
DH
t
INIT
(Note 11)
t
BLC
(Notes 11, 12)
t
RB
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power−up
Byte Load Cycle Time
WE Low to RDY/BUSY Low
0
100
0
0
110
0
0
110
60
0
5
0.05
10
100
220
Min
Max
5
0
100
0
0
150
10
10
150
100
0
5
0.1
10
100
220
28LV65−20
Min
Max
5
0
100
0
0
150
10
10
150
100
0
5
0.1
10
100
220
28LV65−25
Min
Max
5
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t
BLC
max. stops the timer.
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