CAT25C01/02/04/08/16
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
s
10 MHz SPI compatible
s
1.8 to 6.0 volt operation
s
Hardware and software protection
s
Zero standby current
s
Low power CMOS technology
s
SPI modes (0,0 & 1,1)*
s
Commercial, industrial, automotive and
H
LOGEN
FR
A
EE
LE
s
1,000,000 program/erase cycles
s
100 year data retention
s
Self-timed write cycle
A
D
F
R
E
E
TM
s
8-pin DIP/SOIC, 8/14-pin TSSOP and 8-pin MSOP
s
16/32-byte page write buffer
s
Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
extended temperature ranges
DESCRIPTION
The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces
device power requirements. The CAT25C01/02/04
features a 16-byte page write buffer. The 25C08/16
features a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The
HOLD
pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C01/02/04/08/16 is designed
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/14-pin
TSSOP packages.
PIN CONFIGURATION
TSSOP Package (U14, Y14)
CS
SO
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
SOIC Package (S, V)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
DIP Package (P, L)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
TSSOP Package (U, Y)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
MSOP Package (R, Z)*
CS
SO
WP
VSS
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
*CAT25C01/02 only
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
NC
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
E
2
PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
25C128 F02
*Other SPI modes available on request.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1016, Rev. L
CAT25C01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)
.................. –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL(5)
V
IH(5)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
5
3
0
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
2.7V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
V
OUT
= 0V to V
CC
,
CS = 0V
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.5V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILMIN
and V
IHMAX
are reference values only and are not tested.
Doc. No. 1016, Rev. L
2
CAT25C01/02/04/08/16
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
A.C. CHARACTERISTICS
Limits
1.8V-6.0V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC(3)
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
500
500
500
150
150
0
250
150
100
100
100
50
50
100
100
10
250
0
75
50
100
100
100
50
50
Min.
50
50
250
250
DC
1
50
2
2
40
40
5
75
0
75
50
2.5V-6.0V
Max.
20
20
75
75
DC
5
50
2
2
40
40
5
40
4.5V-5.5V
Min.
20
20
40
40
DC
10
50
2
2
Max.
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 100pF
C
L
= 50pF
(2)
Test
UNITS Conditions
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
Max. Min.
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C
L
= 50pF
(3) t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
3
Doc. No. 1016, Rev. L
CAT25C01/02/04/08/16
FUNCTIONAL DESCRIPTION
The CAT25C01/02/04/08/16 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C01/02/04/08/16 to
interface directly with many of today’s popular
microcontrollers. The CAT25C01/02/04/08/16 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C01/02/04/08/16. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C01/02/04/08/16. During a
read cycle, data is shifted out on the falling edge of the
serial clock for SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
t
HO
t
DIS
HI-Z
V
OH
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Note:
(1) X=0 for 25C01, 25C02, 25C08, 25C16. X=A8 for 25C04
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1016, Rev. L
4
CAT25C01/02/04/08/16
04/08/16.
CS
high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C01/02/04/08/16 draws ZERO current in the
Standby mode. A high to low transition on
CS
is required
prior to any sequence being initiated. A low to high
transition on
CS
after a valid write sequence is what
initiates an internal write cycle.
and the 25C01/02/04/08/16. Opcodes, byte addresses,
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK for SPI modes (0,0 & 1,1) .
CS
Chip Select
CS:
CS
is the Chip select pin.
CS
low enables the CAT25C01/
02/04/08/16 and
CS
high disables the CAT25C01/02/
BYTE ADDRESS
Device
CAT25C01
CAT25C02
CAT25C04
CAT25C08
CAT25C16
STATUS REGISTER
7
WPEN
6
0
5
1
4
X
Address Significant Bits
A6 - A0
A7 - A0
A7 - A0 (A8 = X bit from Opcode)
A9 - A0
A10 - A0
Address Don't Care Bits
A7
—
—
A15 - A10
A15 - A11
# Address Clock Pulse
8
8
8
16
16
3
BP1
2
BP0
1
WEL
0
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
0
1
Array Address
Protected
None
25C01: 60-7F
25C02: C0-FF
25C04: 180-1FF
25C08: 0300-03FF
25C16: 0600-07FF
25C01: 40-7F
25C02: 80-FF
25C04: 100-1FF
25C08: 0200-03FF
25C16: 0400-07FF
25C01: 00-7F
25C02: 00-FF
25C04: 000-1FF
25C08: 0000-03FF
25C16: 0000-07FF
Protection
No Protection
Quarter Array Protection
1
0
Half Array Protection
1
1
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
5
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
Doc. No. 1016, Rev. L
FPGA/CPLD
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