MA2909/11
APRIL 1995
DS3577-3.4
PRELIMINARY INFORMATION
MA2909/11
RADIATION HARD MICROPROGRAM SEQUENCER
The MA2909/11 Microprogram Sequencer is fully
compatible with the industry standard 2909A and 2911A
components, and forms part of the GPS 2900 Series of
devices. The series offers a building block approach to
microcomputer and controller design, with each device in the
range being expandable to permit efficient emulation of any
microcode machine.
The devices have tristate outputs and have an internal
address register, with all internal registers changing state on
LOW to HIGH clock transition.
The 4-bit slice can cascade to any number of microwords.
Branch input for N-way branches is supported. Additional
features include:
I
4-bit cascadable microprogram counter.
I
4 x 4 file with stack counter supporting nesting
microsubroutines.
I
Zero input for returning to the zero microcode word.
I
Individual OR input for each bit for branching to higher
microinstructions (2909 only).
The 2909 is a 4-bit wide address controller intended for
sequencing through a series of microinstructions contained in
a ROM or PROM. Two 2909s may be interconnected to
generate an 8-bit address (256 words), and three may be used
to generate a 12-bit address (4K words).
The 2909 can select an address from any of four sources:
1) A set of external direct inputs (D);
2) External data from the R inputs, stored in an internal
register;
3) A four-word push/pop stack; or
4) A program counter register (which usually contains the
last address plus one).
The push/pop stack includes certain control lines so that it
can efficiently execute nested subroutine linkages. Each of the
four outputs can be OR’ed with an external input for conditional
skip or branch instructions, and a separate line forces the
outputs to all zeroes. The outputs are three-state.
The 2911 is an identical circuit to the 2909 except the four
OR inputs are removed and the D and R inputs are tied
together.
FEATURES
I
Fully Compatible with Industry Standard 2909A and
2911A Components
I
Radiation Hard CMOS SOS Technology
I
High SEU Immunity
I
High Speed / Low Power
I
Fully TTL Compatible
1
MA2909/11
The 2909/2911 are CMOS SOS microprogram sequencers
intended for use in high-speed microprocessor applications.
The device is a cascadable 4-bit slice such that two devices
allow addressing of up to 256 words of microprogram and
three devices allow addressing of up to 4K words of
microprogram. A detailed logic diagram is shown in figure 1.
The device contains a four input multiplexer that is used to
select either the address register, direct inputs, microprogram
counter, or file as the source of the next microinstruction
address. This multiplexer is controlled by the S0 and S1 inputs.
The address register consists of four D-type, edge
triggered flip-flops with a common clock enable. When the
address register enable is LOW, new data is entered into the
register on the clock LOW-to-HlGH transition. The address
register is available at the multiplexer as a source for the next
microinstruction address The direct input is a 4-bit field of
inputs to the multiplexer and can be selected as the next
microinstruction address. On the 2911 the direct inputs are
also used as inputs to the register. This allows an N-way
branch where N is any word in the microcode.
The 2909/2911 contains a microprogram counter (µPC)
that is composed of a 4-bit incrementer followed by a 4bit
register. The incrementer has carry-in (C
n
) and carry-out (C
n
+
4) such that cascading to larger word lengths is straight
forward. The µPC can be used in either of two ways. When the
least significant carry-in to the incrementer is HIGH, the
microprogram register is loaded on the next clock cycle with
the current Y output word plus one (Y + 1
§
µPC). Thus
sequential microinstructions can be executed. If this least
significant C
n
is LOW, the incrementer passes the Y output
word unmodified and the microprgram register is loaded with
the same Y word on the next clock cycle (Y
§
µPC). Thus, the
same microinstruction can be executed any number of times
by using the 4x4 file (stack). The file is used to provide return
address linkage when executing microsubroutines. The file
contains a built-in stack pointer (SP) which always points to the
last file word written. This allows stack reference operations
(looping) to be performed without a push or pop.
The stack pointer operates as an up/down counter with
separate push/pop and file enable inputs. When the file enable
input is LOW and the push/pop input is HIGH, the PUSH
operation is enabled. This causes the stack pointer to
increment and the file to be written with the required return
linkage - the next microinstruction address following the
subroutine jump which initiated the PUSH.
If the file enable input is LOW and the push/pop control is
LOW, a POP operation occurs. This implies the usage of the
return linkage during this cycle and thus a return from
subroutine. The next LOW-to-HlGH clock transition causes the
stack pointer to decrement. If the file enable is HIGH, no action
is taken by the stack pointer regardless of any other input.
The stack pointer linkage is such that any combination of
push, pop or stack references can be achieved. One
microinstruction subroutine can be performed. Since the stack
is 4 words deep, up to four microsubroutines can be nested.
The ZERO input is used to force the four outputs to the
binary zero state. When the ZERO input is LOW all Y outputs
are LOW regardless of any other inputs (except OE). Each Y
output bit also has a separate OR input such that a conditional
logic one can be forced at each Y output. This allows jumping
to different microinstructions on programmed conditions.
The 2909/2911 feature three-state Y outputs. These can
be particularly useful in designs requiring external equipment
to provide automatic checkout of the microprocessor. The
internal control can be placed in the high impedance state and
preprogrammed.
MULTIPLEXER SELECT CODES
Table 1 lists the select codes for the multiplexer. The two
bits applied from the microword register (and additional
combinational logic for branching) determine which data
source contains the address for the next microinstruction. The
contents of the selected source will appear on the Y outputs.
Table 1 also shows the truth table for the output control and for
the control of the push/pop stack. Table 2 shows in detail the
effect of S
0
, S
1
, FE and PUP on the 2909. These four signals
define the address that apears on the Y outputs and what the
state of all the internal registers will be following the clock
LOW-to-HlGH edge. In this illustration, the microprogram
counter is assumed to contain initially some word J, the
address register some word K, and the four words in the push/
pop stack contain R
a
through R
d
.
OR1
X
X
H
L
ZERO
X
L
H
H
OE
H
L
L
L
Y1
Z
L
H
Source selected by S
0
S
1
H = High, L = Low, Z = High Impedance
Table 1a: Output Control
FE
H
L
ZERO
X
H
PUSH-POP stack change
No change
Increment stack pointer, then push
current PC on to STK0
Pop stack (decrement stack pointer)
L
L
H = High, L = Low, X = Irrelevant
Table 1b: Synchronous Stack Control
S
1
S
2
L
L
H
H
L
H
L
H
Source for Y outputs
Microprogram counter
Address/Holding register
Push-Pop stack
Direct inputs
Table 1c: Address Selection
Symbol
µPC
AR
STKO
D
1
3
MA2909/11
Cycle
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
S1
L
L
L
L
L
L
H
H
H
H
H
H
S0
L
-
L
-
L
-
H
-
H
-
H
-
L
-
L
-
L
-
H
-
H
-
H
-
H
X
L
H
L
L
H
X
L
H
L
L
H
X
L
H
L
L
H
X
L
H
FE
L
PUP
L
µPC
J
J+1
J
J+1
J
J+1
J
K+1
J
K+1
J
K+1
J
R
a
+ 1
J
R
a
+ 1
J
R
a
+ 1
J
D+1
J
D+1
J
D+1
REG STK0 STK1 STK2 STK3 Y
OUT
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
R
a
R
b
R
a
J
R
a
R
a
R
a
R
b
R
a
J
R
a
R
a
R
a
R
b
R
a
J
R
a
R
a
R
a
R
b
R
a
J
R
a
R
a
R
b
R
c
R
b
R
a
R
b
R
b
R
b
R
c
R
b
R
a
R
b
R
b
R
b
R
c
R
b
R
a
R
b
R
b
R
b
R
c
R
b
R
a
R
b
R
b
R
c
R
d
R
c
R
b
R
c
R
c
R
c
R
d
R
c
R
b
R
c
R
c
R
c
R
d
R
c
R
b
R
c
R
c
R
c
R
d
R
c
R
b
R
c
R
c
R
d
R
a
R
d
R
c
R
d
R
d
R
d
R
a
R
d
R
c
R
d
R
d
R
d
R
a
R
d
R
c
R
d
R
d
R
d
R
a
R
d
R
c
R
d
R
d
J
-
J
-
J
-
K
-
K
-
K
-
R
a
-
R
a
-
R
a
-
D
-
D
-
D
-
Comment
Pop Stack
Push µPC
Continue
Pop Stack;
Use AR for Address
Push µPC;
Jump to Address in AR
Jump to Address in AR
Jump to Address in
STK0; Pop Stack
Jump to Address in
STK0; Push µPC
Jump to Address in
STK0
Pop Stack;
Jump to Address on D
Jump to Address on D;
Push µPC
Jump to Address on D
Principal Use
End Loop
Set-up Loop
Continue
End Loop
JSR AR
JMP AR
RTS
Stack Ref
(Loop)
End Loop
JSR D
JMP D
1 = High, 0 = Low, X = Irrelevant, Assume C
n
= High
Note: STK0 is the location addressed by the stack pointer
Table 2: Output and Internal Next-Cycle Register States for 2909/2911
Table 3 (Page 5) illustrates the execution of a subroutine
using the 2909. The configuration of Figure 2 is assumed. The
instruction being executed at any given time is the one
contained in the microword register (µWR). The contents of the
µWR also control (indirectly, perhaps) the four signals S0, S1,
FE, and PUP. The starting address of the subroutine is applied
to the D inputs of the 2909 at the appropriate time.
In the column on the left is the sequence of
microinstructions to be executed. At address J+2, the
sequence control portion of the microinstruction contains the
command “Jump to subroutine at A”.
At the time T
2
, this instruction is in the µWR, and the 2909
inputs are set-up to execute the jump and save the return
address. The subroutine address A is applied to the D inputs
from the µWR and appears on the Y outputs. The first
instruction of the subroutine, I(A), is accessed and is at the
inputs of the µWR. On the next clock transition, l(A) is loaded
into the µWR for execution, and the return address J + 3 is
pushed on to the stack. The return instruction is executed at
T
5
. Table 4 is a similar timing chart showing one subroutine
linking to a second, the latter consisting of only one
microinstruction.
4
FPGA/CPLD
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