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Low Noise, Rail-to-Rail,
Differential ADC Driver
AD8139
FEATURES
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
Low harmonic distortion
98 dBc SFDR @ 1 MHz
85 dBc SFDR @ 5 MHz
72 dBc SFDR @ 20 MHz
High speed
410 MHz, 3 dB BW (G = 1)
800 V/μs slew rate
45 ns settling time to 0.01%
69 dB output balance @ 1 MHz
80 dB dc CMRR
Low offset: ±0.5 mV maximum
Low input offset current: 0.5 μA maximum
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in a small SOIC package and an 8-lead LFCSP
APPLICATIONS
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB drivers
Differential cable drivers
FUNCTIONAL BLOCK DIAGRAMS
–IN
1
V
OCM 2
V+
3
+OUT
4
AD8139
8
7
6
5
+IN
NC
V–
04679-001
–OUT
NC = NO CONNECT
Figure 1. 8-Lead SOIC
AD8139
TOP VIEW
(Not to Scale)
–IN 1
V
OCM
2
V+ 3
+OUT 4
NC = NO CONNECT
8 +IN
7 NC
6 V–
5 –OUT
04679-102
Figure 2. 8-Lead LFCSP
GENERAL DESCRIPTION
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high
SFDR, and wide bandwidth, it is an ideal choice for driving
ADCs with resolutions to 18 bits. The AD8139 is easy to apply,
and its internal common-mode feedback architecture allows its
output common-mode voltage to be controlled by the voltage
applied to one pin. The internal feedback loop also provides
outstanding output balance as well as suppression of even-order
harmonic distortion products. Fully differential and single-
ended-to-differential gain configurations are easily realized by
the AD8139. Simple external feedback networks consisting of
four resistors determine the closed-loop gain of the amplifier.
The AD8139 is manufactured on the Analog Devices, Inc.
proprietary, second-generation XFCB process, enabling it to
achieve low levels of distortion with input voltage noise of only
2.25 nV/√Hz.
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
100
INPUT VOLTAGE NOISE (nV/ Hz)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
Figure 3. Input Voltage Noise vs. Frequency
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
04679-078
1
10
AD8139
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
V
S
= ±5 V, V
OCM
= 0 V .................................................................. 3
V
S
= 5 V, V
OCM
= 2.5 V ................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ..............................................9
Test Circuits ................................................................................ 17
Theory of Operation ...................................................................... 18
Typical Connection and Definition of Terms ........................ 18
Applications..................................................................................... 19
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks .................................................................... 19
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
10/07—Rev. A to Rev. B.
Changes to General Description .................................................... 1
Inserted Figure 2; Renumbered Sequentially................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 6 and Layout ....................................................... 8
Inserted Figure 6; Renumbered Sequentially................................ 8
Changes to Figure 30...................................................................... 12
Changes to Layout .......................................................................... 17
Changes to Figure 63...................................................................... 22
Changes to Exposed Paddle (EP) Section ................................... 23
Updated Outline Dimensions ....................................................... 24
8/04—Rev. 0 to Rev. A.
Added 8-Lead LFCSP.........................................................Universal
Changes to General Description .....................................................1
Changes to Figure 2...........................................................................1
Changes to V
S
= ±5 V, V
OCM
= 0 V Specifications .........................3
Changes to V
S
= 5 V, V
OCM
= 2.5 V Specifications.........................5
Changes to Table 4.............................................................................7
Changes to Maximum Power Dissipation Section........................7
Changes to Figure 26 and Figure 29............................................. 12
Inserted Figure 39 and Figure 42.................................................. 14
Changes to Figure 45 to Figure 47................................................ 15
Inserted Figure 48........................................................................... 15
Changes to Figure 52 and Figure 53............................................. 16
Changes to Figure 55 and Figure 56............................................. 17
Changes to Table 6.......................................................................... 19
Changes to Voltage Gain Section ................................................. 19
Changes to Driving a Capacitive Load Section .......................... 22
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions....................................................... 24
5/04—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8139
SPECIFICATIONS
V
S
= ±5 V, V
OCM
= 0 V
T
A
= 25°C, differential gain = 1, R
L, dm
= 1 kΩ, R
F
= R
G
= 200 Ω, unless otherwise noted. T
MIN
to T
MAX
= −40°C to +125°C.
Table 1.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
Noise/Harmonic Performance
SFDR
Conditions
Min
Typ
Max
Unit
V
O, dm
= 0.1 V p-p
V
O, dm
= 2 V p-p
V
O, dm
= 0.1 V p-p
V
O, dm
= 2 V step
V
O, dm
= 2 V step, C
F
= 2 pF
G = 2, V
IN, dm
= 12 V p-p triangle wave
V
O, dm
= 2 V p-p, f
C
= 1 MHz
V
O, dm
= 2 V p-p, f
C
= 5 MHz
V
O, dm
= 2 V p-p, f
C
= 20 MHz
V
O, dm
= 2 V p-p, f
C
= 10.05 MHz ± 0.05 MHz
f = 100 kHz
f = 100 kHz
V
IP
= V
IN
= V
OCM
= 0 V
T
MIN
to T
MAX
T
MIN
to T
MAX
340
210
410
240
45
800
45
30
98
85
72
−90
2.25
2.1
MHz
MHz
MHz
V/μs
ns
ns
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
+500
8.0
0.5
μV
μV/°C
μA
μA
dB
V
kΩ
MΩ
pF
dB
V
V
mA
dB
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC Performance
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
Input Characteristics
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
Output Characteristics
Output Voltage Swing
−500
±150
1.25
2.25
0.12
114
−4
Differential
Common mode
Common mode
∆V
ICM
= ±1 V dc, R
F
= R
G
= 10 kΩ
Each single-ended output, R
F
= R
G
= 10 kΩ
Each single-ended output,
R
L, dm
= open circuit, R
F
= R
G
= 10 kΩ
Each single-ended output
f = 1 MHz
600
1.5
1.2
84
+4
80
−V
S
+ 0.20
−V
S
+ 0.15
+V
S
– 0.20
+V
S
− 0.15
100
−69
Output Current
Output Balance Error
V
OCM
TO V
O, cm
PERFORMANCE
V
OCM
Dynamic Performance
−3 dB Bandwidth
Slew Rate
Gain
V
OCM
Input Characteristics
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
V
O, cm
= 0.1 V p-p
V
O, cm
= 2 V p-p
0.999
−3.8
V
OS, cm
= V
O, cm
− V
OCM
; V
IP
= V
IN
= V
OCM
= 0 V
f = 100 kHz
∆V
OCM
/∆V
O, dm
, ∆V
OCM
= ±1 V
−900
515
250
1.000
1.001
+3.8
MHz
V/μs
V/V
V
MΩ
μV
nV/√Hz
μA
dB
74
3.5
±300
3.5
1.3
88
+900
4.5
Rev. B | Page 3 of 24
AD8139
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
−PSRR
OPERATING TEMPERATURE RANGE
Conditions
Min
+4.5
Change in +V
S
= ±1 V
Change in −V
S
= ±1 V
95
95
−40
24.5
112
109
Typ
Max
±6
25.5
Unit
V
mA
dB
dB
°C
+125
Rev. B | Page 4 of 24
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