Hitachi SuperH RISC engine
SH7751 Series
SH7751, SH7751R
Hardware Manual
ADE-602-201B
Rev. 3.0
4/11/2002
Hitachi, Ltd.
Cautions
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Preface
The SH-4 (SH7751 Series (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4
CPU and is also equipped with peripheral functions necessary for configuring a user system.
The SH7751 Series is built in with a variety of peripheral functions such as cache memory,
memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two
serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC),
bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of
multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous
DRAM and PCMCIA.
Target Readers:
This manual is designed for use by people who design application systems using
the SH7751 or SH7751R.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
This hardware manual contains revisions related to the addition of R-mask functionality. Be sure
to check the text for the updated content.
Purpose:
This manual provides the information of the hardware functions and electrical
characteristics of the SH7751 and SH7751R.
The SH-4 Programming Manual contains detailed information of executable instructions. Please
read the Programming Manual together with this manual.
How to Use the Book:
To understand general functions
Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
To understanding CPU functions
Refer to the separate SH-4 Programming Manual.
Explanatory Note:
Bit sequence: upper bit at left, and lower bit at right
List of Related Documents:
The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.hitachisemiconductor.com/)
Rev. 3.0, 04/02, page iii of xxxviii
User manuals for SH7751 and SH7751R
Name of Document
SH7751 Series Hardware Manual
SH-4 Programming Manual
Document No.
This manual
ADE-602-156
User manuals for development tools
Name of Document
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual
Simulator/Debugger User’s Manual
Hitachi Embedded Workshop User’s Manual
Document No.
ADE-702-246
ADE-702-186
ADE-702-201
Rev. 3.0, 04/02, page iv of xxxviii
Contents
Section 1
1.1
1.2
1.3
1.4
Overview
...........................................................................................................
SH7751 Series Features.....................................................................................................
Block Diagram ..................................................................................................................
Pin Arrangement ...............................................................................................................
Pin Functions.....................................................................................................................
1.4.1 Pin Functions (256-Pin QFP) ...............................................................................
1.4.2 Pin Functions (256-Pin BGA) ..............................................................................
1
1
10
11
13
13
24
Section 2
2.1
2.2
Programming Model
...................................................................................... 35
35
36
36
39
41
43
44
46
47
47
48
49
2.3
2.4
2.5
2.6
2.7
Data Formats .....................................................................................................................
Register Configuration ......................................................................................................
2.2.1 Privileged Mode and Banks .................................................................................
2.2.2 General Registers .................................................................................................
2.2.3 Floating-Point Registers .......................................................................................
2.2.4 Control Registers..................................................................................................
2.2.5 System Registers ..................................................................................................
Memory-Mapped Registers ...............................................................................................
Data Format in Registers ...................................................................................................
Data Formats in Memory ..................................................................................................
Processor States.................................................................................................................
Processor Modes................................................................................................................
Section 3
3.1
Memory Management Unit (MMU)
......................................................... 51
51
51
51
54
54
55
58
58
61
62
63
63
64
64
65
65
3.2
3.3
3.4
Overview ...........................................................................................................................
3.1.1 Features ................................................................................................................
3.1.2 Role of the MMU .................................................................................................
3.1.3 Register Configuration .........................................................................................
3.1.4 Caution .................................................................................................................
Register Descriptions.........................................................................................................
Address Space ...................................................................................................................
3.3.1 Physical Address Space........................................................................................
3.3.2 External Memory Space .......................................................................................
3.3.3 Virtual Address Space ..........................................................................................
3.3.4 On-Chip RAM Space ...........................................................................................
3.3.5 Address Translation..............................................................................................
3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode....................
3.3.7 Address Space Identifier (ASID)..........................................................................
TLB Functions...................................................................................................................
3.4.1 Unified TLB (UTLB) Configuration....................................................................
Rev. 3.0, 04/02, page v of xxxviii