19-3925; Rev 1; 4/07
KIT
ATION
EVALU
BLE
AVAILA
Dual, 96Msps, 14-Bit, IF/Baseband ADC
General Description
Features
♦
Direct IF Sampling Up to 350MHz
♦
Excellent Dynamic Performance
73dB/72.2dB SNR at f
IN
= 70MHz/175MHz
83.5dBc/78.8dBc SFDR at f
IN
= 70MHz/175MHz
♦
3.3V Low-Power Operation
980mW (Differential Clock Mode)
952mW (Single-Ended Clock Mode)
♦
Fully Differential or Single-Ended Analog Input
♦
Adjustable Differential Analog Input Voltage
♦
750MHz Input Bandwidth
♦
Adjustable, Internal or External, Shared Reference
♦
Differential or Single-Ended Clock
♦
Accepts 25% to 75% Clock Duty Cycle
♦
User-Selectable DIV2 and DIV4 Clock Modes
♦
Power-Down Mode
♦
CMOS Outputs in Two’s Complement or Gray
Code
♦
Out-of-Range and Data-Valid Indicators
♦
Small, 68-Pin Thin QFN Package
(10mm x 10mm x 0.8mm)
♦
12-Bit, Pin-Compatible Version Available
(MAX12529)
♦
Evaluation Kit Available (Order MAX12559EVKIT)
MAX12559
The MAX12559 is a dual, 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12559 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 980mW while delivering a typical 72.2dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 350MHz. In addition to low oper-
ating power, the MAX12559 features a 0.5mW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12559 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12559
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12559 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help to reduce the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12559 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12559 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12529 data sheet. See the
Selector Guide
for
more selections.
Ordering Information
PART
MAX12559ETK-D
TEMP RANGE PIN-PACKAGE
PKG
CODE
-40°C to +85°C 68 Thin QFN-EP* T6800-4
MAX12559ETK+D -40°C to +85°C 68 Thin QFN-EP* T6800-4
*EP
= Exposed paddle.
+Denotes
lead-free package.
D = Dry pack.
Selector Guide
PART
MAX12559
MAX12558
MAX12557
MAX12529
MAX12528
MAX12527
SAMPLING RATE
(Msps)
96
80
65
96
80
65
RESOLUTION
(Bits)
14
14
14
12
12
12
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual, 96Msps, 14-Bit, IF/Baseband ADC
MAX12559
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND.................................................................-0.3V to +3.6V
OV
DD
to GND............-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
INAP, INAN to GND....-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
INBP, INBN to GND....-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
CLKP, CLKN to
GND ........................-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFIN, REFOUT
to GND ..................-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFAP, REFAN,
COMA to GND ......-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFBP, REFBN,
COMB to GND ......-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,
DIV4 to GND .........-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
D0A–D13A, D0B–D13B, DAV,
DORA, DORB to GND..............................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
68-Pin Thin QFN, 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C) ....................................4000mW
Operating Temperature Range................................-40°C to +85°C
Junction Temperature ...........................................................+150°C
Storage Temperature Range .................................-65°C to +150°C
Lead Temperature (soldering, 10s)......................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -1dBFS (differential),
DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 96MHz (50% duty cycle), T
A
=
-40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUTS (INAP, INAN, INBP, INBN)
Differential Input Voltage Range
Common-Mode Input Voltage
Analog Input Resistance
R
IN
C
PAR
Analog Input Capacitance
C
SAMPLE
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS (V
IN
= -1dBFS)
Small-Signal Noise Floor
SSNF
Input at -35dBFS
f
IN
= 3MHz
Signal-to-Noise Ratio
SNR
f
IN
= 48MHz
f
IN
= 70MHz
f
IN
= 175MHz
69.3
74.5
70.5
76.3
74.3
73.9
73
72.2
dB
dBFS
Figure 5
8
f
CLK
96
5
MHz
MHz
Clock
Cycles
Switched capacitance,
each input, Figure 3
4.5
Each input, Figure 3
Fixed capacitance to ground,
each input, Figure 3
V
DIFF
Differential or single-ended inputs
±1.024
V
DD
/ 2
2.3
2
pF
V
V
kΩ
External reference, V
REFIN
= 2.048V
INL
DNL
f
IN
= 3MHz
f
IN
= 3MHz
14
±2.6
±0.65
±0.05
±0.4
±0.7
±5
Bits
LSB
LSB
%FSR
%FSR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -1dBFS (differential),
DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 96MHz (50% duty cycle), T
A
=
-40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
f
IN
= 3MHz
Signal-to-Noise Plus Distortion
SINAD
f
IN
= 48MHz
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Spurious-Free Dynamic Range
SFDR
f
IN
= 48MHz
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Total Harmonic Distortion
THD
f
IN
= 48MHz
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Second Harmonic
HD2
f
IN
= 48MHz
f
IN
= 70MHz
f
IN
= 175MHz
f
IN
= 3MHz
Third Harmonic
HD3
f
IN
= 48MHz
f
IN
= 70MHz
f
IN
= 175MHz
3rd-Order Intermodulation
Distortion
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Output Noise
f
IN1
= 69MHz at A
IN1
= -7dBFS,
f
IN2
= 72MHz at A
IN2
= -7dBFS
f
IN1
= 173MHz at A
IN1
= -7dBFS,
f
IN2
= 177MHz at A
IN2
= -7dBFS
FPBW
t
AD
t
AJ
n
OUT
INAP = INAN = COMA,
INBP = INBN = COMB
Input at -0.2dBFS, -3dB rolloff
Figure 5
69
65.3
72.2
CONDITIONS
MIN
68.3
TYP
73.7
72.6
72.2
71.2
84.6
81.6
83.5
78.8
-82.1
-78.5
-80.3
-77.8
-85.9
-82.4
-86.1
-78.8
-89.4
-86.6
-84.4
-88.6
-82
dBc
-86
750
1.2
< 0.1
0.9
MHz
ns
ps
RMS
LSB
RMS
dBc
dBc
-66.3
-69.8
dBc
dBc
dB
MAX
UNITS
MAX12559
IM3
_______________________________________________________________________________________
3
Dual, 96Msps, 14-Bit, IF/Baseband ADC
MAX12559
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -1dBFS (differential),
DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 96MHz (50% duty cycle), T
A
=
-40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Overdrive Recovery Time
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Gain Matching
Offset Matching
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage
REFOUT Load Regulation
REFOUT Temperature Coefficient
REFOUT Short-Circuit Current
TC
REF
Short to V
DD
—sinking
Short to GND—sourcing
V
REFOUT
-1mA < I
REFOUT
< +1mA
2.000
2.048
35
55
0.24
2.1
2.080
V
mV/mA
ppm/°C
mA
f
INA
or f
INB
= 70MHz at -1dBFS
f
INA
or f
INB
= 175MHz at -1dBFS
90
83
±0.02
±0.01
±0.1
dB
dB
%FSR
SYMBOL
CONDITIONS
±10% beyond full scale
MIN
TYP
1
MAX
UNITS
Clock
Cycle
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
V
REFAP
/V
REFAN
/V
COMA
and V
REFBP
/V
REFBN
/V
COMB
are generated internally)
REFIN Input Voltage
REFIN Input Resistance
COM_ Output Voltage
REF_P Output Voltage
REF_N Output Voltage
Differential Reference Voltage
Differential Reference
Temperature Coefficient
V
REFIN
R
REFIN
V
COMA
V
COMB
V
REFAP
V
REFBP
V
REFAN
V
REFBN
V
REFA
V
REFB
TC
REF
V
COM_
= V
DD
/ 2
V
REF_P
= V
DD
/ 2 + (V
REFIN
x 3/8)
V
REF_N
= V
DD
/ 2 - (V
REFIN
x 3/8)
V
REF_
= V
REF_P
- V
REF_N
1.440
1.60
2.048
> 50
1.65
2.418
0.882
1.536
40
1.600
1.70
V
MΩ
V
V
V
V
ppm/°C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
REFAP
/V
REFAN
/V
COMA
and V
REFBP
/V
REFBN
/V
COMB
are applied
externally, V
COMA
= V
COMB
= V
DD
/ 2)
REF_P Input Voltage
REF_N Input Voltage
COM_ Input Voltage
Differential Reference Voltage
V
REFAP
V
REFBP
V
REFAN
V
REFBN
V
COM_
V
REFA
V
REFB
V
REF_P
- V
COM_
V
REF_N
- V
COM_
V
COM_
= V
DD
/ 2
V
REF_
= V
REF_P
- V
REF_N
= V
REFIN
x 3/4
+0.768
-0.768
1.65
1.536
V
V
V
V
4
_______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -1dBFS (differential),
DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 96MHz (50% duty cycle), T
A
=
-40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
REF_P Sink Current
REF_N Source Current
COM_ Sink Current
REF_P, REF_N Capacitance
COM_ Capacitance
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold
Minimum Differential Clock Input
Voltage Swing
Differential Input Common-Mode
Voltage
CLKP, CLKN Input Resistance
CLKP, CLKN Input Capacitance
R
CLK
C
CLK
0.8 x
OV
DD
0.2 x
OV
DD
±5
±5
5
D0A–D13A, D0B–D13B, DORA, DORB:
I
SINK
= 200µA
DAV: I
SINK
= 600µA
D0A–D13A, D0B–D13B, DORA, DORB:
I
SOURCE
= 200µA
DAV: I
SOURCE
= 600µA
Tri-State Leakage Current
(Note 2)
I
LEAK
OV
DD
applied to input
Input connected to ground
OV
DD
-
0.2
V
OV
DD
-
0.2
±5
±5
µA
V
IH
V
IL
DIFFCLK/SECLK = GND, CLKN = GND
DIFFCLK/SECLK = GND, CLKN = GND
DIFFCLK/SECLK = OV
DD
DIFFCLK/SECLK = OV
DD
Figure 4
0.2
V
DD
/ 2
5
2
0.8 x
V
DD
0.2 x
V
DD
V
V
V
P-P
V
kΩ
pF
SYMBOL
I
REFAP
I
REFBP
I
REFAN
I
REFBN
I
COMA
I
COMB
C
REF_P
,
C
REF_N
C
COM_
CONDITIONS
V
REF_P
= 2.418V
V
REF_N
= 0.882V
V
COM_
= 1.65V
MIN
TYP
1.2
0.85
0.85
13
6
MAX
UNITS
mA
mA
mA
pF
pF
MAX12559
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4, SHREF)
Input High Threshold
Input Low Threshold
Input Leakage Current
Digital Input Capacitance
C
DIN
V
IH
V
IL
OV
DD
applied to input
Input connected to ground
V
V
µA
pF
DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)
Output-Voltage Low
V
OL
0.2
0.2
V
Output-Voltage High
V
OH
_______________________________________________________________________________________
5
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