512K x 32 FLASH Module
PUMA 2/77F16006/A/B - 70/90/12
Issue 5.1 May 2001
Description
Available in PGA (PUMA 2) and Gullwing
(PUMA77) footprints.
The PUMA **F16006 is a 16MBit FLASH module
user configurable as 512K x 32, 1M x 16 or 2M x 8.
The device is available with access times of 70, 90
and 120ns.
The device utilises, 5V only FLASH, to simplify
circuit design. Sector size is 64K Byte with
hardware protection available on any number of
sectors.
The device features 10,000 Write erase cycle
compatibility and 10 year data retention.
All options may be screened in accordance with
MIL-STD-883.
Block Diagram
PUMA 77F16006
A0~A18
/OE
/WE
512K x 8
FLASH
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
FLASH
512K
x 8
FLASH
512K x 8
FLASH
PUMA 2F16006/B, 77F16006A/B
A0~A18
/OE
/WE4
/WE3
/WE2
/WE1
512K x 8
FLASH
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
FLASH
512K
x 8
FLASH
512K x 8
FLASH
Features
• 16 Megabit FLASH module.
• Fast Access Times of 70/90/120 ns.
• Output Configurable as 32 / 16 / 8 bit wide.
• Operating Power
880/456/242mW (Max).
Low Power Standby
33mW (Max).
• Automatic Write/Erase by Embedded Algorithm -
end of Write/Erase indicated by /DATA Polling and
Toggle Bit.
• Flexible Sector Erase Architecture - 64K byte
sector size, with hardware protection of any
number of sectors.
• Erase/Write Cycle Endurance 100,000 (Min.) -
E variant.
• 10 year Data Retention.
• May be screened in accordance with
MIL-STD-883.
Pin Definitions
See page 2, 3 & 4.
Pin Functions
Description
Signal
A0~A18
D0~D31
/CS1~4
/WE1~4
/OE
NC
V
CC
V
SS
Package Details
PUMA 2 -JEDEC 66 pin Ceramic PGA Package.
Max. Dimensions (mm) - 27.69 x 27.69 x 6.86
PUMA 77 -JEDEC 68 Leaded GullWing Package
Max. Dimensions (mm) - 25.15 x 25.15 x 5.44
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power
Ground
Absolute Maximum Ratings
(1)
DC Operating Conditions
Parameter
Voltage on any pin relative to V
SS
Supply Voltage
(2)
(3)
V
SS
Symbol
V
T
V
A9
T
STG
Min
-0.6
-0.6
-0.6
-65
Typ
-
-
-
-
Max
+6.0
+6.0
+13.5
+150
Unit
V
V
V
O
Voltage on A9 relative to
Storage Temperature
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied.
(2) Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is V
CC
+0.5V During
transitions voltage may overshoot by +1V for up to 10ns
(3) Minimum DC input voltage on A9 is -0.5V during voltage transitions, A9 may overshoot V
SS
to -1V for periods of
up
to 10ns, maximum DC input voltage in A9 is 13.5V which may overshoot to 14.0V for periods up to 10ns
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial
)
(Industrial)
(Military)
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
Min
4.5
2.0
-0.5
0
-40
-55
Typ
5.0
-
-
-
-
-
Max
5.5
V
CC
+0.5
0.8
70
85
125
Unit
V
V
V
O
O
O
C
C
C
(I Suffix)
(M\MB Suffix)
DC Electrical Characteristics
(V
CC
=5V+10%, T
A
=-55
O
C to 125
O
C)
Parameter
Input Leakage Current
Address, /OE
A9 Input Leakage Current
Output Leakage Current
V
CC
Operating Current
32 Bit
16 Bit
8 Bit
Symbol Test Condition
I
LI1
I
LI2
I
LO
I
CCO32
V
CC
=V
CC
max, V
IN
=0V or V
CC
V
CC
=V
CC
max, A9=12.5V
V
CC
=V
CC
max, V
OUT
=0V or V
CC
/CS =V
IL
,/OE=V
IH
,I
OUT
=0mA,
f=6MHz
(1)
Min
-
-
-
-
-
-
-
-
-
(1)
Typ Max Unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+10
400
+10
160
83
44
240
123
64
6
12.5
0.45
-
4.2
µ
A
µ
A
µ
A
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
I
CCO16
As Above
I
CCO8
I
CCP32
I
CCP16
I
CCP8
I
SB1
V
ID
V
OL
V
OH1
V
LKO
As Above
Programming In Progress
As Above
As Above
V
CC
=V
CC
max,/CS=V
IH
/OE=V
IH
V
CC
=5.0V
I
OL
=12mA, V
CC
= V
CC
Min
I
OH
=-2.5mA, V
CC
= V
CC
Min
V
CC
Program Erase Current
32 Bit
16 Bit
8 Bit
Standby Supply Current
Autoselect/Sector Protect Voltage
Output Voltage Low
Output Voltage High
Low V
CC
Lock-Out Voltage
Notes
-
11.5
-
2.4
3.2
(1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
PAGE 5
Issue 5.1 May 2001
FPGA/CPLD
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