FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12548-3E
8-bit Original Microcontroller
CMOS
F
2
MC-8L MB89530 Series
MB89537/537C/538/538C
MB89F538L/P538/PV530
s
DESCRIPTION
The MB89530 series is a one-chip microcontroller featuring the F
2
MC-8L core supporting low-voltage and high-
speed operation. Built-in peripheral functions include timers, serial interface, A/D converter, and external interrupt.
This product is an ideal general-purpose one-chip microcontroller for a wide variety of applications from household
to industrial equipment, as well as use in portable devices.
s
FEATURES
• Wide range of package options
•
QFP package (1mm pitch)
•
Two types of LQFP packages (0.5mm pitch, 0.65mm pitch)
•
SH-DIP package
•
BCC package (0.5mm pitch)
• Low voltage, high-speed operating capability
•
Minimum instruction execution time 0.32
µs
(at base oscillator 12.5MHz)
• F
2
MC-8L CPU Core
•
Instruction set optimized for controller operation
•
Multiplication/division instructions
•
16-bit calculation
•
Branching instructions with bit testing
•
Bit operation instructions, etc.
• Five timer systems
•
8-bit PWM timer with 2 channels (usable as either interval timer of PWM timer)
•
Pulse width count timer (supports continuous measurement or remote control receiving applications)
•
16-bit timer counter
•
21-bit time base timer
•
Watch prescaler (17-bit)
• UART
•
Synchronous or asynchronous operation, switchable
• 2 serial interfaces (serial I/O)
•
Selection of transfer direction (specify MSB first or LSB first) for communication with a variety of devices
(Continued)
MB89530 Series
(Continued)
• 10-bit A/D converter (8 channels)
•
External clock input for startup support (except for MB89F538L)
•
Time base timer output for startup support
• Pulse generators (PPG) with 2-program capability
•
6-bit PPG with selection of pulse width and pulse period
•
12-bit PPG (2 channels) with selection of pulse width and pulse period
• I
2
C interface circuits
• External interrupt 1 (single-clock : 4 channels, dual-clock : 3 channels)
•
4 or 3 independent inputs, release enabled from standby mode (includes edge detection function)
• External interrupt 2 (except for MB89F538L : 8 channels, MB89F538L : 7 channels)
•
8 or 7 independent inputs, release enabled form standby mode (includes level edge detection function)
• Standby modes (low power consumption modes)
•
Stop mode (oscillator stops, virtually no power consumed)
•
Sleep mode (CPU stops, power consumption reduced to one-third)
•
Sub clock mode
•
Watch mode
• Watchdog timer reset
• I/O ports
•
Maximum port
single-clock : except for MB89F538L : 53
MB89F538L
: 52
dual-clock
: except for MB89F538L : 51
MB89F538L
: 50
•
38 general-purpose I/O ports (CMOS) (MB89F538L : 37)
•
2 general-purpose I/O ports (N-ch open drain)
•
8 general-purpose output ports (N-ch open drain)
•
General-purpose input ports(CMOS)single-clock : except for MB89F538L : 5
dual-clock : except for MB89F538L : 3
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MB89530 Series
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PACKAGES
64-pin, Plastic SH-DIP
64-pin, Plastic LQFP
64-pin, Plastic QFP
(DIP-64P-M01)
64-pin, Plastic LQFP
(FPT-64P-M03)
64-pin, Ceramic MDIP
(FPT-64P-M06)
64-pin, Ceramic MQFP
(FPT-64P-M09)
(MDP-64C-P02)
64-pin, Plastic BCC
(MQP-64C-P01)
(LCC-64P-M19)
(LCC-64P-M16)
3
MB89530 Series
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PRODUCT LINEUP
Part number
Parameter
Type
MB89537/
537C
MB89538/
538C
MB89F538L
FLASH
48 K
×
8-bit
(built-in FLASH
memory)
(write from
general purpose
EPROM writer)
MB89P538
One-time
programmable
48 K
×
8-bit
(built-in ROM)
(write from
general purpose
EPROM writer)
MB89PV530
Evaluation
Mass produced (Mask ROM)
ROM capacity
32 K
×
8-bit
(built-in ROM)
48 K
×
8-bit
(built-in ROM)
48 K
×
8-bit
(external
ROM) *
2
RAM capacity
Operating voltage
1 K
×
8-bit
2.2 V to 3.6 V*
1
(MB89537/538/
537C/538C)
Basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Minimum interrupt processing time
Input ports
2 K
×
8-bit
2.4 V to 3.6 V*
1
: 136
: 8-bits
: 1 bit to 3 bits
: 1, 8, 16-bits
: 0.32
µs /
12.5 MHz
: 2.88
µs /
12.5 MHz
2.7 V to 5.5 V
CPU functions
Ports
Peripheral functions
: single-clock 5 (4 also usable as external interrupts)
dual-clock 3 (3 also usable as external interrupts)
Output-only ports (N-ch open drain)
: 8 (8 also usable as ADC input)
I/O ports (N-ch open drain)
: 2 (2 also usable as SO2/SDA or SI2/SCL)
I/O ports (CMOS)
: 38 (21 have no other function)
(except for MB89F538L)
I/O ports (CMOS)
: 37 (21 have no other function)
(MB89F538L)
Total (except for MB89F538L) : single-clock 53, 2system clock 51
Total (MB89F538L)
: single-clock 52, 2system clock 50
21 bits
Time base timer Interrupt periods at main clock oscillation frequency of 12.5MHz
(approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms)
Watchdog timer
Reset period of approx. 167.8 ms to 335.6 ms at mail clock frequency of 12.5 MHz
Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz.
8-bit interval timer operation
(supports square wave output, operating clock period : 1, 8, 16, 64 t
inst
*
3
)
Pulse width measurement with 8-bit resolution (conversion period : 2
8
t
inst
*
3
to 2
8
×
64 t
inst
*
3
)
2 channels (can also be used as interval timer, can also be used as ch1 output and ch2
count clock)
Interval times at 17-bit sub clock base frequency of 32.768 kHz
(approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s)
PWM timer
Watch prescaler
(Continued)
4
MB89530 Series
(Continued)
Part number
Parameter
MB89537/537C
MB89538/538C
MB89F538L
MB89P538
MB89PV530
Pulse width
count timer
8-bit one-shot timer operation
(supports underflow output, operating clock period : 1, 4, 32 t
inst
*
3
, external)
8-bit reload timer operation
(supports square wave output, operating clock period : 1, 4, 32 t
inst
*
3
, external)
8-bit pulse width measurement operation
(continuous measurement, H width measurement, L width measurement, rise-to-rise, fall-
to-fall, H width measurement and rise-to-rise)
16-bit timer operation (operating clock period : 1 t
inst
*
3
, external)
16-bit event counter operation (select rising, falling, or both edges)
16-bit
×
1 ch
8 bit length, Selection of LSB first or MSB first, Transfer clock (2, 8, 32 t
inst
*
3
, external)
CLK synchronous/CLK asynchronous data transfer capability (8, 9 bit with parity bit, or 7,8
bit without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8 bit with parity bit,
or 5, 7, 8, 9 bit without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
External clock output, 2-channel 8-bit PWM timer output also available for baud rate set-
tings.
Single-clock : 4-channel independent, dual-clock : 3-channel independent
Selection of rising, falling, or both edge detection.
Can be used for recovery from standby mode (edge detection also available in stop mode) .
Except for MB89F538L : 8-channel independent L level detection, MB89F538L : 7-channel
independent L level detection
Can be used for recovery from standby mode.
Can generate square wave signals with programmable period.
6-bit
×
1 channel or 12-bit
×
2 channels.
16-bit timer/
counter
Serial I/O
UART/SIO
Peripheral functions
UART
External
interrupt 1
External
interrupt 2
6-bit PPG,
12-bit PPG
1-channel , compatible with Intel System Administrator bus version 1.0 and Philips I
2
C
I
2
C bus interface specifications.
2-line communications (on MB89PV530/P538/F538L/537C/538C)
10-bit resolution
×
8 channels.
A/D conversion functions (conversion time : 60 t
inst
*
3
)
Supports repeated calls from external clock (except for MB89F538L)
Supports repeated calls from internal clock.
Standard voltage input provided (AVR)
Sleep mode, stop mode, sub clock mode, watch mode.
CMOS
A/D converter
Standby modes
(power saving
modes)
Process
*1 : Depends on operating frequency.
*2 : Using external ROM and MBM27C512.
*3 : t
inst
represents instruction execution time. This can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock
cycle or 1/2 of the sub clock cycle.
Note : MB89537/538 have no built-in I
2
C functions.
To use I
2
C functions, choose the MB89PV530/P538/F538L/MB89537C/538C.
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FPGA/CPLD
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