FUJITSU SEMICONDUCTOR
DATA SHEET
8-bit Proprietary Microcontroller
CMOS
F
2
MC-8L MB89560H Series
MB89567H/567HC/P568/PV560
s
DESCRIPTION
The MB89560H series has been developed as a general-purpose version of the F
2
MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as
I
2
C interface, timers, 2 ch PWM timers, 8/16-bit timer, 21bit timebase timer, 8 bit PWC timer , 17-bit Watch
prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster),
Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt.
*: F
2
MC stands for FUJITSU Flexible Microcontroller.
s
FEATURES
•
•
•
•
•
•
•
•
•
F
2
MC-8L family CPU core
Low-voltage operation (when an A/D converter is not used)
Low current consumption (applicable to the dual-clock system)
Minimum execution time: 0.32
µs
at 12.5 MHz
I
2
C interface circuit
LCD controller/driver : 24 segments x 4 commons (max. 96 pixels, duty LCD mode and Static LCD mode)
LCD booster function (option)
Wild register (max. 6 different address locations)
10-bit A/D converter: 8 channels
(Continued)
s
PACKAGE
80-pin Plastic LQFP
80-pin Plastic QFP
80-pin Plastic LQFP
80-pin Ceramic MQFP
(FPT-80P-M05)
(FPT-80P-M06)
(FPT-80P-M11)
(MQP-80C-P01)
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
MB89560H Series
(Continued)
• Three types of Serial Interface:
High Speed UART (
Transfer rate from 300 to 192000 bps /10 MHz main clock)
8-bit Serial I/O (SIO)
UART/SIO
• Two type of Programmable Pulse Generator(PPG) : 6-bit PPG and 12-bit PPG
• Six types of timer
8 bit PWM 2 channels timers
8/16 bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel)
21bit timebase timer
8 bit PWC timer operation
Watch prescaler(17 bits)
Watch-dog timer
• I/O ports: max. 50 channels
• External interrupt 1: 8 channels
• External interrupt 2 (wake-up function): 4 channels
• Low-power consumption modes (stop mode, sleep mode, and watch mode)
• LQFP-80 and QFP-80 package
• CMOS technology
s
PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
RAM size
CPU functions
MB89567H
MB89567HC
MB89P568
OTP
48 K
×
8 bits
(internal PROM)
MB89PV560
Piggy-back
56 K
×
8 bits
(external ROM)
1K
×
8 bits
Mass production products
(mask ROM products)
32 K
×
8 bits
(internal mask ROM)
1K
×
8 bits
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Minimum interrupt processing time:
General-purpose I/O ports (N-channel open drain)
General-purpose I/O ports (CMOS)
Total
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, 16 bits
: 0.4
µs/10
MHz
: 3.6
µs/10
MHz
: 20 pins (2 shared with I
2
C inputs, 16 shared
with LCD, 2 shared with other resources)
: 30 pins (shared with resources)
: 50 pins
Ports
21-bit timebase
timer
Watchdog timer
Watch prescaler
8/16-bit timer/
counter
8-bit PWM 2 ch
timer
21 bits
Interrupt cycle: 2
11
, 2
13
, 2
16
or 2
20
t
inst
*
5
Reset generate cycle: min. 2
20
t
inst
for main clock, min. 2
13
t
inst
for sub clock
17 bits
Interrupt cycle: 0.50s, 1.00s, 2.00s, 4.00s/32.768 KHz for subclock
Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own
independent operating clock cycle), or as one 16-bit timer/counter
In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and
square wave output capable
8-bit interval timer operation (square wave output capable, operating clock cycle: 1, 8, 16, 64 t
inst
)
8-bit resolution PWM operation (conversion cycle: 256 to 256 x 64 t
inst
)
8/16-bit timer/counter output for counter clock selectability
2
MB89560H Series
Part number
Parameter
MB89567H
MB89567HC
MB89P568
MB89PV560
PWC timer
8-bit timer operation (count clock cycle: 1, 4, 32 t
inst
)
8-bit reload timer operation (toggle output possible, operating clock cycle: 1 - 32 t
inst
)
8-bit pulse width measurement (continuous measurement possible: High and Low widths, H to H, L
to L, period & H at same time and High & rising to rising)
10-bit resolution × 8 channels
A/D conversion function (conversion time: 60 t
inst
)
Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable.
Internal 6-bit counter
Pulse width and cycle are program selectable
Internal 12-bit counter
Pulse width and cycle are program selectable
Not
Available
1 channel
Use a 2-wire protocol to communicate with other device
10-bit A/D con-
verter*
2
6 bit PPG
12 bit PPG
I
2
C interface*
4
High speed UART
Transfer data length: 4, 6, 7, 8 bits
Transfer rate (300 to 192000 bps /10 MHz main clock)
support sub-clock mode
Transfer data length: 7, 8 bits for UART, 8 bits for SIO
Transfer rate (1201 to 78125 bps / 10 MHz main clock)
support sub-clock mode
8 bits, LSB first/MSB first selectability
One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks:
2, 8, 32 t
inst
)
Common output: 4 (max.)
Segment output: 24 (max.)
LCD driving power (bias) pins: 4
LCD display RAM size: 12 bytes (24 × 4 bits, max. 96 pixels)
Duty LCD mode and Static LCD mode
Booster for LCD driving: option
Dividing resister for LCD driving: Built-in*
1
Maximum of 6-byte data can be assigned in 6 different address.
Used to replace any data in the ROM when specific address and data are assigned in Wild register.
Wild register can be set up by using different communication methods through the device.
8 independent channels (interrupt vector, request flag, request output enable)
Edge selectability (rising/falling)
Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.)
4 channels (“L” level interrupts, independent input enable).
Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop mode.)
Sleep mode, stop mode and clock mode
CMOS
3.5 V to 5.5 V
3.5 V to 5.5 V
2.7 to 5.5 V
2.7 to 5.5 V*
3
UART/SIO
8-bit serial I/O
LCD
Wild register
External interrupt 1
(wake-up function)
External interrupt 2
(wake-up function)
Standby mode
Process
Operating voltage*
* :Varies with conditions such as the operating frequency. (See “s Electrical Characteristics.”)
*1 : When booster is used, the bias is reduced by 1/3. it can be selected by mask option.
*2 : When the A/D converter is used, operating voltage must be 3.5V to 5.5V.
*3 : Use MBM27C512-20 as the external ROM (operating voltage: 4.5 V to 5.5 V)
*4 : I
2
C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I
2
C specification.
*5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main
clock mode is selected , or 1/2 of the subclock if subclock mode is selected
3
MB89560H Series
s
PACKAGE AND CORRESPONDING PRODUCTS
Package
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
MB89567H
MB89567HC
MB89P568-101
MB89P568-102
MB89PV560-101
MB89PV560-102
s
DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually
be used. Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket.
• When operating at low speed, the current consumed by the one-time PROM product is greater than for the mask ROM
product. However, the current consumption is roughly the same in sleep or stop mode.
• (For more information, see “s Electrical Characteristics.”)
3. Mask Options
The functions available as options and the method of specifying options differ between products.
Before using options check “s Mask Options.”
4. Functionalities different between products in MB89560H series
Functionalities
MB89567H
MB89567HC
MB89P568
MB89PV560
Power-on reset wait time
Wait time for
external reset in stop/sub/clock mode
or
wait time for external interrupt trigger
recover from main stop mode
Port pin pullup resistors
AD conversion time
I C noise cancelling circuit
2
Regulator stab. time +
Regulator recovery. time +
Osc. stab. time
Regulator stab. time +
Osc. stab. time
Osc. stab. time
Regulator recovery time +
Osc. stab. time
Osc. stab. time
Selectable by software.
60 t
INST
*
—
Always available independent of
ICCR:DMBP bit selection.
Not available.
33 t
INST
*
Not available when
ICCR:DMBP bit is
asserted.
Note: For more information on t
INST
see “s Electrical Characteristics (4) Instruction cycles"
* : Instruction cycle
4
MB89560H Series
s
PIN ASSIGNMENT
(Top view)
SEG07
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P64/SEG22
P67/SEG23
AVR
AVcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
SEG06
SEG05
SEG04
SEG03
SEG02
SEG01
SEG00
COM3
COM2
COM1
COM0
V3
V2
V1
V0
C0
C1
P47/PWC
P46/UI/SI1
P45/UO/SO1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P44/UCK/SCK1
P43/PWM2/PPG2
P42/PWM1/EC1
P41/HCK/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
Vcc
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
X1A
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
AVss
P17/INT17
P16/INT16
P15/INT15
P14/INT14
P13/INT13
P12/INT12
P11/INT11
C
P10/INT10
RST
X0A
(FPT-80P-M05)
(FPT-80P-M11)
5
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
