FINAL
COM’L: H-7/10/15/20
IND: H-10/15/20
PALCE26V12 Family
28-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s
28-pin versatile PAL programmable logic
device architecture
s
Electrically erasable CMOS technology
provides half power (only 115 mA) at high
speed (7.5 ns propagation delay)
s
14 dedicated inputs and 12 input/output
macrocells for architectural flexibility
s
Macrocells can be registered or combinatorial,
and active high or active low
s
Varied product term distribution allows up to
16 product terms per output
s
Two clock inputs for independent functions
s
Global asynchronous reset and synchronous
preset for initialization
s
Register preload for testability and built-in
register reset on power-up
s
Space-efficient 28-pin SKINNYDIP and PLCC
packages
s
Center VCC and GND pins to improve signal
characteristics
s
Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE26V12 is a 28-pin version of the popular
PAL22V10 architecture. Built with low-power, high-
speed, electrically-erasable CMOS technology, the
PALCE26V12 offers many unique advantages.
Device logic is automatically configured according to
the user’s design specification. Design is simplified by
design software, allowing automatic creation of a
programming file based on Boolean or state equations.
The software can also be used to verify the design and
can provide test vectors for the programmed device.
The PALCE26V12 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced
to sum-of-products form, taking advantage of the
very wide input gates available in PAL devices. The
functions are programmed into the device through
electrically-erasable floating-gate cells in the AND logic
array and the macrocells. In the unprogrammed state,
all AND product terms float HIGH. If both true and
complement of any input are connected, the term will be
permanently LOW.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, active high or
active low, with registered I/O possible. The flip-flop can
be clocked by one of two clock inputs. The output
configuration is determined by four bits controlling three
multiplexers in each macrocell.
AMD’s FusionPLD program allows PALCE26V12
designs to be implemented using a wide variety of
popular industry-standard design tools. By working
closely with the FusionPLD partners, AMD certifies that
the tools provide accurate, quality support. By ensuring
that third-party tools are available, costs are lowered
because a designer does not have to buy a complete set
of new tools for each device. The FusionPLD program
also greatly reduces design time since a designer can
use a tool that is already installed and familiar. Please
refer to the PLD Software Reference Guide for certified
development systems and the Programmer Reference
Guide for approved programmers.
2-306
Publication#
16072
Rev.
E
Issue Date:
February 1996
Amendment
/0
AMD
BLOCK DIAGRAM
CLK/I
2
12
I
SYNC.
PRESET
8
8
10
12
14
PROGRAMMABLE
AND ARRAY
(52x150)
16
16
14
12
10
8
8
ASYNC.
RESET
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
16072E-1
CONNECTION DIAGRAMS
Top View
DIP
CLK
2
/I
3
CLK1/I0
I1
I2
CLK2/I3
I4
I5
VCC
I6
I7
I8
I9
I10
I11
I12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
I13
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
GND
I/O5
I/O4
I/O3
I/O2
I/O1
I
4
I
5
V
CC
I
6
I
7
I
8
I
9
5
6
7
8
9
10
11
4
3
PLCC
CLK
1
/I
0
I/O
11
I/O
10
I
1
2
1 28 27 26
25
24
23
22
21
20
19
I/O
9
I/O
8
I/O
7
I/O
6
GND
I/O
5
I/O
4
12 13 14 15 16 17 18
I/O
0
I/O
1
I/O
2
I/O
3
I
10
I
11
I
12
I/O0
16072E-2
Note:
Pin 1 is marked for orientation.
I
13
I
2
16072E-3
PIN DESCRIPTION
CLK
GND
I
I/O
V
CC
=
=
=
=
=
Clock
Ground
Input
Input/Output
Supply Voltage
PALCE26V12 Family
2–307
AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD commercial and industrial programmable logic products are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
PAL
CE 26 V 12 H
-7
P C /4
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF OUTPUTS
POWER
H= Half Power (115 mA I
CC
)
OPTIONAL PROCESSING
Blank = Standard Processing
PROGRAMMING DESIGNATOR
/4 = First Revision
(May require programmer
update)
OPERATING CONDITIONS
C = Commercial (0
°
C to +75
°
C)
I = Industrial (–40
°
C to +85
°
C)
PACKAGE TYPE
P = 28-Pin 300 mil Plastic
SKINNYDIP (PD3028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
SPEED
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-15 = 15 ns t
PD
-20 = 20 ns t
PD
Valid Combinations
PALCE26V12H-7
PALCE26V12H-10
PALCE26V12H-15
PALCE26V12H-20
JC
PC, JC, PI, JI
/4
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
2–308
PALCE26V12H-7/10/15/20 (Com’l), H-10/15/20 (Ind)
AMD
FUNCTIONAL DESCRIPTION
The PALCE26V12 has fourteen dedicated input lines,
two of which can be used as clock inputs. Unused inputs
should be tied directly to ground or V
CC
. Buffers for
device inputs and feedbacks have both true and
complementary outputs to provide user-selectable
signal polarity. The inputs drive a programmable AND
logic array, which feeds a fixed OR logic array.
The OR gates feed the twelve I/O macrocells (see
Figure 1). The macrocell allows one of eight potential
output configurations; registered or combinatorial, ac-
tive high or active low, with register or I/O pin feedback
(see Figure 2). In addition, registered configurations can
be clocked by either of the two clock inputs.
The configuration choice is made according to the
user’s design specification and corresponding program-
ming of the configuration bits S0–S3
(
see Table 1).
Multiplexer controls initially float to V
CC
(1) through a
programmable cell, selecting the “1” path through the
multiplexer. Programming the cell connects the control
line to GND (0), selecting the “0” path.
OE
AR CLK 1
P1
AR
D Q
1
0
CLK 2
SP
1
S3*
S2
0
S1
Q
SP
1
1
0
0
0
1
0
1
S0
Pn
n = 8,8,10,12,14,16
* When S 3 = 1 (unprogrammed) the feedback is selected by S 1.
When S 3 = 0 (programmed), the feedback is the opposite of
that selected by S 1.
16072E-4
Figure 1. PALCE26V12 Macrocell
Registered or Combinatorial
Each macrocell of the PALCE26V12 includes a D-type
flip-flop for data storage and synchronization. The
flip-flop is loaded on the LOW-to-HIGH edge of the
selected clock input. Any macrocell can be configured
as combinatorial by selecting a multiplexer path that
bypasses the flip-flop. Bypass is controlled by bit S1.
Table 1. Macrocell Configuration Table
S3
1
1
1
1
0
0
0
0
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Output Configuration
Registered Output and Feedback,
Active Low
Registered Output and Feedback,
Active High
Combinatorial I/O, Active Low
Combinatorial I/O, Active High
Registered I/O, Active Low
Registered I/O, Active High
Combinatorial Output, Registered
Feedback, Active Low
Combinatorial Output, Registered
Feedback, Active High
Programmable Clock
The clock input for any flip-flop can be selected to be
from either pin 1 or pin 4. A 2:1 multiplexer controlled by
bit S2 determines the clock input.
Programmable Feedback
A 2:1 multiplexer allows the user to determine whether
the macrocell feedback comes from the flip-flop or
from the I/O pin, independent of whether the output is
registered or combinatorial. Thus, registered outputs
may have internal register feedback for higher speed
(f
MAX
internal), or I/O feedback for use of the pin as a
direct input (f
MAX
external). Combinatorial outputs may
have I/O feedback, either for use of the signal in other
equations or for use as another direct input, or register
feedback.
1 = Unprogrammed EE bit
0 = Programmed EE bit
S2
1
0
Clock Input
CLK
1
/I
0
CLK
2
/I
3
PALCE26V12 Family
2–309
AMD
The feedback multiplexer is controlled by the same bit
(S1) that controls whether the output is registered or
combinatorial, as on the 22V10, with an additional
control bit (S3) that allows the alternative feedback path
to be selected. When S3 = 1, S1 selects register
feedback for registered outputs (S1 = 0) and I/O
feedback for combinatorial outputs (S1 = 1). When S3 =
0, the opposite is selected: I/O feedback for registered
outputs and register feedback for combinatorial outputs.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system initialization. Outputs of the PALCE26V12 will
be HIGH or LOW depending on whether the output is
active low or active high, respectively. The V
CC
rise must
be monotonic, and the reset delay time is 1000 ns
maximum.
Register Preload
The register on the PALCE26V12 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows
direct loading of arbitrary states, thereby making it
unnecessary to cycle through long test vector se-
quences to reach a desired state. In addition, transitions
from illegal states can be verified by loading illegal
states and observing proper recovery.
Programmable Enable and I/O
Each macrocell has a three-state output buffer con-
trolled by an individual product term. Enable and disable
can be a function of any combination of device inputs or
feedback. The macrocell provides a bidirectional I/O pin
if I/O feedback is selected, and may be configured as a
dedicated input if the buffer is always disabled. This is
accomplished by connecting all inputs to the enable
term, forcing the AND of the complemented inputs to be
always LOW. To permanently enable the outputs, all
inputs are left disconnected from the term (the
unprogrammed state).
Security Bit
After programming and verification, a PALCE26V12
design can be secured by programming the security bit.
Once programmed, this bit defeats readback of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. Pro-
gramming the security bit disables preload, and the
array will read as if every bit is disconnected. The
security bit can only be erased in conjunction with
erasure of the entire pattern.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and
combinatorial outputs. Selection is automatic, based on
the design specification and pin definitions. If the pin
definition and output equation have the same polarity,
the output is programmed to be active high.
Programming and Erasing
The PALCE26V12 can be programmed on standard
logic programmers. It also may be erased to reset a
previously configured device back to its virgin state.
Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
The PALCE26V12 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest
programming yields and post-programming functional
yields in the industry.
Preset/Reset
For initialization, the PALCE26V12 has additional
Preset and Reset product terms. These terms are
connected to all registered outputs. When the Synchro-
nous Preset (SP) product term is asserted high, the
output registers will be loaded with a HIGH or the next
LOW-to-HIGH clock transition. When the Asynchronous
Reset (AR) product term is asserted high, the output
registers will be immediately loaded with a LOW
independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Technology
The high-speed PALCE26V12 is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
2–310
PALCE26V12 Family
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