FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28824-3E
ASSP for Screen Display Control
CMOS
ON-Screen Display Controller
MB90092
s
DESCRIPTION
The MB90092 is the display controller for displaying text and graphics on the TV screen.
The MB90092 incorporates display memory (VRAM), a font memory interface, and a video signal generator,
allowing text and graphics to be displayed in conjunction with a small number of external components.
The MB90092 can provide two screens, called the main screen and the sub-screen, either independently or
overlayed one on top of the other.
The main screen consists of 24 characters by 12 lines and allows data to be set for each character. The sub-
screen consists of 32 characters by 12 lines or up to 32 characters by 16 lines. Data can be set either for each
line in the former configuration or collectively for the entire screen in the latter configuration.
For output of video signals, the MB90092 has the composite video signal, Y/C-separated video signal, and RGB
digital output pins. The MB90092 also has video signal input pins, allowing superimpose display over either
composite video signals and Y/C-separated video signals.
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PACKAGE
80-pin Plastic QFP
(FPT-80P-M06)
MB90092
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FEATURES
• Main Screen Display
• Screen display capacity:24 characters
×
12 lines (up to 288 characters)
• Character dot configuration:24
×
32 dots (per character)
• Character types: 16384 different characters (when using a 16 M bit external clock)
• Character sizes: Standard, double width, double height, double width
×
double height,
quadruple width
×
double height (Setting possible for each line)
• Display position control :Horizontal display position
:Set in 1/3-character units
Vertical display position
:Set in raster units
Line spacing control
:Set in raster units (0 to 15 rasters)
• Display priority control:Capable of controlling display priority over the sub-screen (for each line)
• Sub-Screen Display
Screen display position: Settable horizontally and vertically in 2-dot units
• Normal screen mode:Screen capacity:32 characters
×
12 lines (up to 384 characters)
256 horizontal dots
×
384 vertical dots (graphics characters only) (The
actual display screen depends on the television system and dot clock
frequency.) Normal character/graphic character display selectable for
each line (Header display character code is specified for each line.)
Character string length:Selectable from among 1, 2, 4, 8, 16, 24, and 32 digits
• Full-screen mode
Screen capacity: 32 characters
×
16 lines (up to 512 characters)
256 horizontal dots
×
512 vertical dots
(The actual display screen depends on the television
system and dot clock frequency.)
Virtual screen capacity:Mode A:32 characters
×
16 lines (× 32 screens)
256 horizontal dots
×
512 vertical dots
Mode B:512 characters
×
32 lines
4096 horizontal dots
×
1024 vertical dots
Screen Background Display
Screen background color: 8 colors (set for the entire screen)
Analog Inputs
• Composite video signal input
• Y/C-separated inputs
Analog Outputs
• Composite video signal output
• Y/C-separated outputs
Digital Outputs
• G (Green), R (Red), and B (Blue) output
• VOC (character) output, VOB (character + background) output
• Characters, character background, line background, and screen background each capable of being displayed
in eight colors
Internal Synchronization Control (Video Signal Generator)
• Internal video signal generator supporting the NTSC and PAL systems
• Interlaced/noninterlaced display selectable
(Continued)
2
MB90092
(Continued)
External Synchronization Control
• Separated sync signal input/composite sync signal input selectable
External Interface
• 8-bit serial inputs (3 signal input pins)
Chip select: CS
Serial clock: SCLK
Serial data: SIN
Package
• QFP-80
Miscellaneous
• Internal power-on reset circuit
3
MB90092
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PIN ASSIGNMENT
(TOP VIEW)
XD
EXD
TEST
TSC
V
CC
ADR20
ADR19
ADR18
ADR17
ADR16
ADR15
ADR14
ADR13
ADR12
ADR11
V
SS
TESTI
VOC
VOB
V
SS
B
R
G
CS
SCLK
SIN
V
CC
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
EXS
XS
TEST1
FSCO
CBCK
PDS
V
SS
AV
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
ADR10
ADR9
V
CC
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
V
SS
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
READ
V
CC
AV
CC
1
4
TEST2
TEST3
TEST4
TEST5
AV
SS
AV
SS
YOUT
YIN
AV
CC
2
COUT
CIN
AV
SS
VOUT
VKIN
VKOUT
VIN
(FPT-80P-M06)
MB90092
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PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type
Function
Test signal input pin. Input High level signal during normal operation.
This pin also can be used as a reset signal input pin by Low-level input
to the TEST pin. That is effective only after release of power-on reset.
This pin is a hysteresis input with an internal pull-up resistor.
Character interval signal output pin.
The output signal represents the character dot output interval.
Character/background internal signal output pin.
During internal synchronization control operation, the output signal rep-
resents the character, character background, line background, or screen
background output interval.
Color signal output pins.
These pins output the character, character background, line back-
ground, and screen background color signals.
Chip select pin.
For serial transfer, set this pin to the Low level.
This pin is also used to release a power-on reset.
The pin is a hysteresis input with an internal pull-up resistor.
Shift clock input pin for serial transfer.
This pin is a hysteresis input with an internal pull-up resistor.
Serial data input pin.
The pin is a hysteresis input with an internal pull-up resistor.
External horizontal sync signal input pin.
Input negative logic signal.
This pin can also serve as a composite sync signal input pin depending
on the internal register setting.
The pin is a hysteresis input with an internal pull-up resistor.
External vertical sync signal input pin.
Input negative logic signal.
Input to this pin is disabled when composite sync signal input has been
selected by setting the internal register. The pin is a hysteresis input with
an internal pull-up resistor.
Horizontal sync signal output pin.
This pin can also output composite sync signals depending on the inter-
nal register setting.
The pin outputs the signal (FSC) resulting from dividing the 4FSC clock
frequency by setting the TEST pin to the Low level.
Vertical sync signal output pin.
This pin is fixed at the High level when composite sync signal output has
been selected by setting the internal register.
The pin outputs the dot clock oscillator signal when the TEST pin goes
into Low.
Vertical blanking interval signal output pin.
This pin outputs the Low-level signal in the vertical blanking interval.
1
TESTI
I
B
2
VOC
O
C
3
VOB
O
C
5
6
7
B
R
G
O
C
8
CS
I
B
9
10
SCLK
SIN
I
I
B
B
12
EXHSYN
I
B
13
EXVSYN
I
B
14
HSYNC
O
C
15
VSYNC
O
C
16
VBLNK
O
C
(Continued)
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FPGA/CPLD
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