FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13744-2E
16-bit Proprietary Microcontrollers
CMOS
F
2
MC-16LX MB90350E Series
MB90F351E (S) , MB90F351TE (S) , MB90F352E (S) , MB90F352TE (S) , MB90351E (S) ,
MB90351TE (S) , MB90352E (S) , MB90352TE (S) , MB90F356E (S) , MB90F356TE (S) ,
MB90F357E (S) , MB90F357TE (S) , MB90356E (S) , MB90356TE (S) , MB90357E (S) ,
MB90357TE(S) , MB90V340E-101/102/103/104
■
DESCRIPTION
The MB90350E series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose FUJITSU
16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN
interface, which conforms to CAN standard Version2.0 Part A and Part B, while supporting a very flexible message
buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35
µm
CMOS
technology, Fujitsu now offers on-chip Flash ROM program memory up to 128 Kbytes.
The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major
advantage in terms of EMI and power consumption.
The PLL clock multiplication circuit provides an internal 42 ns instruction execution time from an external 4 MHz
clock. Also, the clock supervisor function can monitor main clock and sub clock independently.
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit,
2 separate 16-bit free-run timers, 2-channel UART and 15-channel 8/10-bit A/D converter built-in.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB90350E Series
■
FEATURES
•
Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed (devices without
S-suffix only) .
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time
multiplied PLL clock).
• Built-in clock modulation circuit
•
16 Mbytes CPU memory space
24-bit internal addressing
•
Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
•
Clock supervisor (MB90x356x and MB90x357x only)
• Main clock or sub clock is monitored independently.
• Internal CR oscillation clock (100 kHz typical) can be used as sub clock.
•
Enhanced high-precision computing with 32-bit accumulator
•
Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
•
Increased processing speed
4-byte instruction queue
•
Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported.
•
Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI
2
OS) : up to 16 channels
• DMA : up to 16 channels
•
Low power consumption (standby) mode
• Sleep mode (a mode that stops CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
•
Process
CMOS technology
•
I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix : devices that correspond to sub clock)
- 51 ports (devices with S-suffix : devices that do not correspond to sub clock)
(Continued)
2
MB90350E Series
•
Sub clock pin (X0A, X1A)
• Yes (using the external oscillation) : devices without S-suffix
• No (using the sub clock mode at internal CR oscillation) : devices with S-suffix
•
Timer
• Timebase timer, watch timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit
×
10 channels or 16-bit
×
6 channels
• 16-bit reload timer : 2 channels (only Evaluation products has 4 channels)
• 16- bit input/output timer
- 16-bit free-run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU4/5/6/7, OCU4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
•
FULL-CAN interface : 1 channel
• Compliant with CAN standard Version2.0 Part A and Part B
• 16 message buffers are built-in
• CAN wake-up function
•
UART (LIN/SCI) : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available.
•
I
2
C interface*
1
: 1 channel
Up to 400 kbps transfer rate
•
DTP/External interrupt : 8 channels, CAN wakeup : 1 channel
Module for activation of extended intelligent I/O service (EI
2
OS), DMA, and generation of external interrupt by
external input.
•
Delay interrupt generator module
Generates interrupt request for task switching.
•
8/10-bit A/D converter : 15 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3
µs
(at 24-MHz machine clock, including sampling time)
•
Program patch function
• Address matching detection for 6 address pointers.
•
Capable of changing input voltage level for port
• Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)
• TTL level (corresponds to external bus pins only, initial level of these pins is TTL in external bus mode)
•
Low voltage/CPU operation detection reset (devices with T-suffix)
• Detects low voltage (4.0 V
±
0.3 V) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(approx. 262 ms : external 4 MHz)
•
Dual operation Flash memory
• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
•
Supported T
A
= +
125
°C
The maximum operating frequency is 24 MHz*
2
: (at T
A
= +125 °C)
.
(Continued)
3
MB90350E Series
(Continued)
•
Flash security function
• Protects the content of Flash memory
(MB90F352x, MB90F357x only)
•
External bus interface
• 4 Mbytes external memory space
MB90F351E(S), MB90F351TE(S), MB90F352E(S), MB90F352TE(S) : External bus Interface can not be used
in internal vector mode. It can be used only in external vector mode.
*1 : I
2
C license :
Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined by
Philips.
*2 : If used exceeding T
A
= +
105
°C,
be sure to contact Fujitsu for reliability limitations.
4
MB90350E Series
■
PRODUCT LINEUP1 (Without Clock supervisor function)
•Flash memory products
Part Number
Parameter
Type
CPU
System clock
ROM
RAM
Emulator-specific
power supply*
1
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Clock supervisor
Low voltage/CPU
operation detection
reset
Operating voltage
Operating
temperature
Package
No
Yes
Yes
No
No
Yes
MB90F351E,
MB90F352E
MB90F351TE,
MB90F352TE
MB90F351ES,
MB90F352ES
MB90F351TES,
MB90F352TES
Flash memory products
F
2
MC-16LX CPU
PLL clock multiplication circuit (×1,
×2, ×3, ×4, ×6,
1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL
×
6)
64 Kbytes Flash memory : MB90F351E(S), MB90F351TE(S)
128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the
same time) : MB90F352E(S), MB90F352TE(S)
4 Kbytes
⎯
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
−40 °C
to
+125 °C
LQFP-64
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3
µs
includes sample time (per one channel)
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
=
Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7.
UART
I
2
C (400 kbps)
A/D converter
16-bit reload timer
(2 channels)
16-bit I/O timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .
Operation clock frequency : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
=
Machine clock frequency)
4 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
5
16-bit output
compare
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
