FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13729-1E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90370/375 Series
MB90372/F372/F377/V370
s
DESCRIPTION
The MB90370/375 series is a line of general-purpose, 16-bit microcontrollers designed for those applications
which require high-speed real-time processing. The instruction set is designed to be optimized for controller
applications which inheriting the AT architecture of F
2
MC-16LX series and allow a wide range of control tasks to
be processed efficiently at high speed.
A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices
in computer system. Moreover, SMbus compliant I
2
C*
2
, comparator for battery control and A/D converter imple-
ments the smart battery control. With these features, the MB90370/375 series matches itself as keyboard con-
troller with smart battery control.
(Continued)
s
PACKAGE
144-pin plastic LQFP
(FPT-144P-M12)
MB90370/375 Series
(Continued)
While inheriting the AT architecture of the F
2
MC*
1
family, the instruction set for the F
2
MC-16LX CPU core of the
MB90370/375 series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which
enables processing of long-word data.
*1 : F
2
MC stands for FUJITSU Flexible Microcontroller and a registered trademark of FUJITSU LIMITED.
*2 : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined
by Philips.
s
FEATURES
•
Clock
• Embedded PLL clock multiplication circuit
• Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz to 16 MHz) .
• Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at
V
CC
of 3.3 V)
•
CPU addressing space of 16M bytes
• Internal 24-bit addressing
•
Instruction set optimized for controller applications
• Rich data types (bit, byte, word, long word)
• Rich addressing mode (23 types)
• High code efficiency
• Enhanced precision calculation realized by the 32-bit accumulator
•
Instruction set designed for high level language (C) and multi-task operations
• Adoption of system stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
•
Program patch function (2 address pointer)
•
Improved execution speed
• 4-byte instruction queue
•
Powerful interrupt function
• Priority level programmable : 8 levels
• 32 factors of stronger interrupt function
•
Automatic data transmission function independent of CPU operation
• Extended intelligent I/O service function (EI
2
OS)
• Maximum 16 channels
•
Low-power consumption (standby) mode
• Sleep mode (mode in which CPU operating clock is stopped)
• Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped)
• Stop mode (mode in which all oscillations are stopped)
• CPU intermittent operation mode
• Watch mode
•
Package
• LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
•
Process
• CMOS technology
2
MB90370/375 Series
s
PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
RAM size
MB90V370
—
—
15.7K Bytes
MB90F372
MB90F377
MB90372
Mask ROM
Flash type ROM
64K Bytes
6K Bytes
CPU function
Number of instruction : 351
Minimum execution time : 62.5 ns
/
4 MHz (PLL
×
4)
Addressing mode : 23
Data bit length : 1, 8, 16 bits
Maximum memory space : 16M Bytes
I/O port (N-channel) : 16
I/O port (CMOS) : 72
I/O port (CMOS with pull-up control) : 32
Total : 120
Reload timer : 4 channels
Reload mode, single-shot mode or event count mode selectable
PPG timer : 3 channels
PWM mode or single-shot mode selectable
Bit decoder : 1 channel
Parity generator : 1 channel
Selectable odd/even parity
PS/2 interface : 3 channels
4 selectable sampling clocks
LPC bus interface : 1 channel
Universal peripheral Interface : 4 channels
GA20 output control : for UPI channel 0 only
Data buffer array : 48 bytes
Yes
No
Yes
No
I/O port
16-bit reload timer
16-bit PPG timer
Bit decoder
Parity generator
PS/2 interface
LPC interface
LPC Standby (able to work
in Stop/TBT/Watch mode)
Serial IRQ controller
Serial IRQ request : 6 channels
LPC clock monitor
/
control
With full-duplex double buffer (variable data length)
Clock asynchronized or clock synchronized transmission (with start and stop bits)
can be selectively used
I
2
C (SMbus compliant) : 1 channel
Support I
2
C bus of Philips and the SMbus proposed by Intel
Selectable packet error check
Timeout detection function
No
No
Yes
No
UART
I
2
C
PC Arbitration under
a paticular condition*
2
(Continued)
3
MB90370/375 Series
(Continued)
Part number
Parameter
MB90V370
MB90F372
MB90F377
MB90372
Multi-address I
2
C
Multi-address I
2
C (SMbus compliant) : 1 channel
Support I
2
C bus of Philips and the SMbus proposed by Intel
Selectable packet error check
Timeout detection function
6 addresses support
ALERT function
Three bus connection routes can be switched by I
2
C
/
multi-address I
2
C
A comparator that can change the hysteresis width is contained
Battery voltage, mounting/dismounting and instantaneous interruption can be de-
tected
Parallel and serial charging/discharging
6 independent channels
Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level
8 independent channels
Causes : “L” level
8/10-bit resolution : 12 channels
Conversion time : Less than 6.13
µs
(16 MHz internal clock)
8-bit resolution : 2 channels
Up to 9 SEG
×
4 COM
Without LCD
Selectable LCD output or CMOS I/O port controller/driver
Same as
MB90F372
Bridge circuit
Comparator
External
interrupt
Key-on wake-up
interrupt
8/10-bit A/D
converter
8-bit D/A
converter
LCD controller/driver*
3
Low-power
consumption
Process
Package
Operating voltage
Stop mode
/
Sleep mode
/
CPU intermittent operation mode
/
Watch mode
CMOS
PGA256
LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
3.0 V to 3.6 V @ 16 MHz *
1
*1 : Varies with conditions such as the operating frequency (see Section “s ELECTRICAL CHARACTERISTICS”) ,
Assurance for the MB90V370 is given only for operation with a tool at power supply voltage of 3.0 V to 3.6 V,
an operating temperature of 0
°C
to +25
°C,
and an operating frequency of 1 MHz to 16 MHz.
*2 : I
2
C can detect the arbitration lost when another I
2
C starts another communication at the same time.
*3 : After reset, PF5 to PF7 serve as general purpose I/O pins in MB90F377; however, these pins serve as V1, V2
and V3 function in other products.
4
MB90370/375 Series
s
PACKAGE AND CORRESPONDING PRODUCTS
Package
PGA256
FPT-144P-M12
: Available
X : Not available
Note : For more information about each package, see Section “s PACKAGE DIMENSIONS”.
X
MB90V370
MB90F372
X
MB90F377
X
MB90372
X
s
DIFFERENCES AMONG PRODUCTS
Memory size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V370 does not have an internal ROM, however, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V370, images from FF4000
H
to FFFFFF
H
are mapped to bank 00, and FF0000
H
to FF3FFF
H
are
mapped to bank FF only. (This setting can be changed by the development tool configuration.)
• In the MB90372/F372, images from FF4000
H
to FFFFFF
H
are mapped to bank 00, and FF0000
H
to FF3FFF
H
are mapped to bank FF only.
5
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