FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13722-5E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90480/485 Series
MB90F481/F482/487/F488/V480/V485
s
DESCRIPTION
The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in
consumer devices and other applications requiring high-speed real-time processing.
The F
2
MC-16LX CPU core instruction set retains the AT architecture of the F
2
MC*
1
family, with additional instruc-
tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete
bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.
The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial
interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-counter, PWC timer, I
2
C*
2
interface, DTP/external
interrupt, chip select, and 16-bit reload timer.
*1 : F
2
MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU, Ltd.
*2 : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C stand a Specification as defined by
Philips.
s
PACKAGES
100-pin plastic QFP
100-pin plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90480/485 Series
s
FEATURES
• Clock
Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied
×
4 (25 MHz internal operating
frequency/3.3 V
±
0.3 V)
62.5 ns/4 MHz base frequency multiplied
×
4 (16 MHz internal operating
frequency/3.0 V
±
0.3 V) PLL clock multiplier
• Maximum memory space: 16 Mbyte
• Instruction set optimized for controller applications
Supported data types (bit, byte, word, or long word)
Typical addressing modes (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
32-bit accumulator for enhanced high-precision calculation
• Instruction set designed for high-level language (C) and multi-task operations
System stack pointer adopted
Instruction set compatibility and barrel shift instructions
• Non-multiplex bus/multiplex bus compatible
• Enhanced execution speed
4 byte instruction queue
• Enhanced interrupt functions
8 levels setting with programmable priority, 8 external interrupts
• Data transmission function (µDMA)
Up to 16 channels
• Embedded ROM
Flash versions : 192 KB, 256 KB, MASK versions : 192 KB
• Embedded RAM
Flash versions : 4 KB, 6 KB, 10 KB, MASK versions : 10 KB
• General purpose ports
Up to 84 ports
(Except MB90V480 : Includes 16 ports with input pull-up resistance, 16 ports with output open drain settings)
• A/D converter
8-channel RC sequential comparison type (10-bit resolution, 3.68
µs
conversion time (at 25 MHz) )
• I
2
C interface (MB90485 series only) : 1channel, P76/P77 Nch OD pin (without Pch)
Do not apply high voltage in excess of recommended operating ranges
to the Nch open drain pin (with Pch) in MB90V485.
•
µPG
(MB90485 series only) : 1 channel
• UART: 1 channel
• I/O expanded serial interface (SIO) : 2 channels
• 8/16-bit PPG: 3 channels (with 8-bit
×
6 channel/16-bit
×
3 channel mode switching function)
• 8/16-bit up/down timer: 1 channel (with 8-bit
×
2 channel/16-bit
×
1-channel mode switching function)
• PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three)
• 3 V/5 V I/F pin (MB90485 series only)
P20 to P27, P30 to P37, P40 to P47, P70 to P77
• 16-bit reload timer: 1 channel
• 16-bit I/O timer: 2-channel input capture, 6-channel output compare, 1-channel free run timer
• On chip dual clock generator system
• Low-power consumption mode
With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode
• Packages: QFP 100/LQFP 100
• Process: CMOS technology
• Power supply voltage: 3 V, single source (some ports can be operated by 5 V power supply at MB90485 series)
2
MB90480/485 Series
s
PRODUCT LINEUP
•
MB90480 series
Part number
Item
ROM size
RAM size
MB90F481
FLASH 192 KB
4 KB
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
MB90F482
FLASH 256 KB
6 KB
MB90V480
16 KB
CPU function
: 351
: 8-bit, 16-bit
: 1 byte to 7 bytes
: 1-bit, 8-bits, 16-bits
: 40 ns (25 MHz machine clock)
Ports
UART
8/16-bit PPG timer
8/16-bit up/down
counter/timer
16-bit free run timer
16-bit
Output compare
I/O timers (OCU)
Input capture
(ICU)
DTP/external interrupt circuit
Extended I/O serial interface
Timebase timer
General-purpose I/O ports: up to 84
General-purpose I/O ports (CMOS output)
General-purpose I/O ports (with pull-up resistance)
General-purpose I/O ports (N-ch open drain)
1 channel, start-stop synchronized
8-bit
×
6 channel/16-bit
×
3 channel
6 event input pins, 8-bit up/down counters: 2
8-bit reload/compare registers: 2
Number of channels: 1
Overflow interrupt
Number of channels: 6
Pin input factor: A match signal of compare register
Number of channels: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of external interrupt channels: 8 (edge or level detection)
2 channels, embedded
18-bit counter
Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
Conversion resolution: 8/10-bit, switchable
One-shot conversion mode (converts selected channel 1 time only)
Scan conversion mode (conversion of multiple consecutive channels,
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase
timer mode
CMOS
FLASH model
Not included security function
Evaluation model,
user terminal,
3 V/5 V versions
Included
A/D converter
Watchdog timer
Low-power consumption
(standby) modes
Process
Type
Emulator power supply*
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
switching) about details.
3
MB90480/485 Series
•
MB90485 series
Part number
Item
ROM size
RAM size
MB90487*
1
192 KB
10 KB
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
MB90F488*
2
FLASH 256 KB
10 KB
MB90V485*
1
16 KB
CPU function
: 351
: 8-bit, 16-bit
: 1 byte to 7 bytes
: 1-bit, 8-bits, 16-bits
: 40 ns (25 MHz machine clock)
Ports
General-purpose I/O ports: up to 84
General-purpose I/O ports (CMOS output)
General-purpose I/O ports (with pull-up resistance)
General-purpose I/O ports (N-ch open drain)
1 channel, start-stop synchronized
8-bit
×
6 channel/16-bit
×
3 channel
6 event input pins, 8-bit up/down counters: 2
8-bit reload/compare registers: 2
Number of channels: 1
Overflow interrupt
Number of channels: 6
Pin input factor: A match signal of compare register
Number of channels: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of external interrupt channels: 8 (edge or level detection)
2 channels, embedded
1 ch
1 ch
3 ch
18-bit counter
Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
Conversion resolution: 8/10-bit, switchable
One-shot conversion mode (converts selected channel 1 time only)
Scan conversion mode (conversion of multiple consecutive channels,
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase
timer mode
CMOS
UART
8/16-bit PPG timer
8/16-bit up/down
counter/timer
16-bit free run timer
16-bit
Output compare
I/O timers (OCU)
Input capture
(ICU)
DTP/external interrupt circuit
Extended I/O serial interface
I
2
C interface *
4
µPG
PWC
Timebase timer
A/D converter
Watchdog timer
Low-power consumption
(standby) modes
Process
(Continued)
4
MB90480/485 Series
(Continued)
Part number
Item
Type
Emulator power supply*
5
*1 : Under development
*2 : Being planed
*3 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and
P70 to P77.
*4 : P76/P77 pins are Nch open drain pins (without Pch) at built-in I
2
C. However, MB90V485 uses the Nch open
drain pin (with Pch) .
*5 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
Note : As for MB90V485, Input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/µPG/I
2
C become
CMOS input.
MB90487*
1
MASK model
3 V/5 V power supply*
3
MB90F488*
2
FLASH model
3 V/5 V power supply*
3
Included security function
MB90V485*
1
Evaluation model
3 V/5 V power supply*
3
Included
5
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