FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13722-8E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90480/485 Series
MB90F481/F482/487B/488B/483C
MB90F488B/F489B/V480/V485B
■
DESCRIPTION
The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in
consumer devices and other applications requiring high-speed real-time processing.
The F
2
MC-16LX CPU core instruction set retains the AT architecture of the F
2
MC*
1
family, with additional instruc-
tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete
bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.
The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial
interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I
2
C*
2
interface, DTP/
external interrupt, chip select, and 16-bit reload timer.
*1 : F
2
MC is the abbreviation for FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C standard a Specification as defined
by Philips.
■
FEATURES
• Clock
Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied
×
4 (25 MHz internal operating
frequency/3.3 V
±
0.3 V)
62.5 ns/4 MHz base frequency multiplied
×
4 (16 MHz internal operating
frequency/3.0 V
±
0.3 V) PLL clock multiplier
• Maximum memory space: 16 Mbytes
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
MB90480/485 Series
(Continued)
• Instruction set optimized for controller applications
Supported data types (bit, byte, word, or long word)
Typical addressing modes (23 types)
32-bit accumulator for enhanced high-precision calculation
Enhanced signed multiplication/division instruction and RETI instruction functions
• Instruction set designed for high-level programming language (C) and multi-task operations
System stack pointer adopted
Instruction set symmetry and barrel shift instructions
• Non-multiplex bus/multiplex bus compatible
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt functions
8 levels setting with programmable priority, 8 external interrupts
• Data transfer function (µDMAC)
Up to 16 channels
• Embedded ROM
Flash versions : 192 Kbytes, 256 Kbytes, 384 Kbytes, MASK versions : 192 Kbytes, 256 Kbytes
• Embedded RAM
Flash versions : 4 Kbytes, 6 Kbytes, 10 Kbytes, 24 Kbytes, MASK versions : 10 Kbytes, 16 Kbytes
• General purpose ports
Up to 84 ports
(Includes 16 ports with input pull-up resistance settings, 16 ports with output open-drain settings)
• A/D converter
8-channel RC sequential comparison type (10-bit resolution, 3.68
µs
conversion time (at 25 MHz) )
• I
2
C interface (MB90485 series only) : 1channel, P76/P77 N-ch open drain pin (without P-ch)
Do not apply high voltage in excess of recommended operating ranges
to the N-ch open drain pin (with P-ch) in MB90V485B.
•
µPG
(MB90485 series only) : 1 channel
• UART : 1 channel
• Extended I/O serial interface (SIO) : 2 channels
• 8/16-bit PPG : 3 channels (with 8-bit
×
6 channel/16-bit
×
3 channel mode switching function)
• 8/16-bit up/down counter/timer: 1 channel (with 8-bit
×
2 channels/16-bit
×
1-channel mode switching function)
• PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three)
• 3 V/5 V I/F pin (MB90485 series only)
P20 to P27, P30 to P37, P40 to P47, P70 to P77
• 16-bit reload timer : 1 channel
• 16-bit I/O timer : 2 channels input capture, 6 channels output compare, 1 channel free run timer
• On chip dual clock generator system
• Low-power consumption mode
With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode
• Packages : QFP 100/LQFP 100
• Process : CMOS technology
• Power supply voltage : 3 V, single power supply (some ports can be operated by 5 V power supply at MB90485
series)
2
MB90480/485 Series
■
PRODUCT LINEUP
•
MB90480 series
Part number
Item
Classification
ROM size
RAM size
MB90F481
MB90F482
MB90V480
Flash memory product
Evaluation product
192 Kbytes
256 Kbytes
⎯
4 Kbytes
6 Kbytes
16 Kbytes
Number of instructions : 351
Instruction bit length
: 8-bit, 16-bit
CPU function
Instruction length
: 1 byte to 7 bytes
Data bit length
: 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 40 ns (25 MHz machine clock)
General-purpose I/O ports: up to 84
General-purpose I/O ports (CMOS output)
Ports
General-purpose I/O ports (with pull-up resistance)
General-purpose I/O ports (N-ch open drain output)
UART
1 channel, start-stop synchronized
8/16-bit PPG
8-bit
×
6 channels/16-bit
×
3 channels
8/16-bit up/down
Event input pins : 6, 8-bit up/down counters : 2
counter/timer
8-bit reload/compare registers : 2
Number of channels : 1
16-bit free run timer
Overflow interrupt
Output compare
Number of channels : 6
16-bit
I/O timers (OCU)
Pin input factor : A match signal of compare register
Input capture
Number of channels : 2
(ICU)
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external interrupt circuit
Number of external interrupt pin channels : 8 (edge or level detection)
Extended I/O serial interface
Embedded 2 channels
18-bit counter
Timebase timer
Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
Conversion resolution : 8/10-bit, switchable
One-shot conversion mode (converts selected channel 1 time only)
Scan conversion mode (conversion of multiple consecutive channels,
A/D converter
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
Watchdog timer
(minimum value, at 4 MHz base oscillator)
Low-power consumption
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode,
(standby) modes
timebase timer mode
Process
CMOS
User pin*
1
,
Type
Not included security function
3 V/5 V versions
⎯
Included
Emulator power supply*
2
*1 : User pin : P20 to P27, P30 to P37, P40 to P47, P70 to P77
*2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
switching) about details.
Note : Ensure that you must write to Flash at V
CC
=
3.13 V to 3.60 V (3.3 V
+
10%,
−5%)
.
3
MB90480/485 Series
•
MB90485 series
Part number
Item
Classification
ROM size
RAM size
MB90487B
MB90488B MB90F488B MB90V485B MB90F489B
Flash
memory
product
256 Kbytes
10 Kbytes
Evaluation
product
⎯
16 Kbytes
Flash
memory
product
384 Kbytes
24 Kbytes
MB90483C
MASK ROM
product
256 Kbytes
16 Kbytes
MASK ROM product
192 Kbytes
10 Kbytes
256 Kbytes
10 Kbytes
CPU function
Number of instructions : 351
Instruction bit length
: 8-bit, 16-bit
Instruction length
: 1 byte to 7 bytes
Data bit length
: 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 40 ns (25 MHz machine clock)
General-purpose I/O ports : up to 84
General-purpose I/O ports (CMOS output)
General-purpose I/O ports (with pull-up resistance)
General-purpose I/O ports (N-ch open drain output)
1 channel, start-stop synchronized
8-bit
×
6 channels/16-bit
×
3 channels
Event input pins : 6, 8-bit up/down counters : 2
8-bit reload/compare registers : 2
Ports
UART
8/16-bit PPG
8/16-bit up/down
counter/timer
16-bit free run Number of channels : 1
timer
Overflow interrupt
16-bit
I/O
timers
Output
compare
(OCU)
Input capture
(ICU)
DTP/external interrupt
circuit
Extended I/O serial
interface
I
2
C interface*
2
µPG
PWC
Timebase timer
Number of channels : 6
Pin input factor: A match signal of compare register
Number of channels : 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of external interrupt pin channels: 8 (edge or level detection)
Embedded 2 channels
1 channel
1 channel
3 channels
18-bit counter
Interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
Conversion resolution : 8/10-bit, switchable
One-shot conversion mode (converts selected channel 1 time only)
Scan conversion mode (conversion of multiple consecutive channels,
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
(Continued)
A/D converter
4
MB90480/485 Series
(Continued)
Part number
Item
Watchdog timer
Low-power
consumption (standby)
modes
Process
MB90487B
MB90488B
MB90F488B MB90V485B MB90F489B
MB90483C
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase
timer mode
CMOS
3 V/5 V
power
supply*
1
⎯
3 V/5 V
power
supply*
1
⎯
3 V/5 V power
supply*
1
Included
security
function
⎯
3 V/5 V
power
supply*
1
3 V/5 V power
supply*
1
Included
security
function
⎯
3 V/5 V
power
supply*
1
⎯
Type
Emulator power
supply*
3
Included
*1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and
P70 to P77.
*2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I
2
C. However, MB90V485B uses the N-ch open
drain pin (with P-ch) .
*3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
Notes :
•
As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/µPG/I
2
C
become CMOS input.
•
Ensure that you must write to Flash at V
CC
=
3.13 V to 3.60 V (3.3 V
+
10%,
−
5%) .
5
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