FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13713-3E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90495G Series
MB90497G/F497G/F498G/V495G
s
DESCRIPTION
The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed for devices
like consumer electronics, which require high-speed, real-time process control. This series features an on-chip
full-CAN interface.
In addition to being backwards compatible with the F
2
MC* family architecture, the instruction set has been ex-
panded to add support for high-level language instructions, expanded addressing mode, and enhanced multiply/
divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long
word (32-bit) data.
The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit
PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller.
* : F
2
MC is abbreviation for Fujitsu Flexible Microcontroller. F
2
MC is a registered trademark of Fujitsu Limited.
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FEATURES
• Models that support
+125 °C
• Clock
•Built-in PLL clock multiplier circuit
•Choose 1/2 oscillation clock or
×1
to
×4
multiplied oscillation clock (for a 4-MHz oscillation clock, 4 to 16 MHz)
machine (PLL) clock
(Continued)
s
PACKAGES
64-pin plastic QFP
64-pin plastic LQFP
(FPT-64P-M06)
(FPT-64P-M09)
MB90495G Series
(Continued)
•Select subclock behavior (8.192 kHz)
•Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and
×
4 PLL clock)
• 16-MByte CPU memory space
•24-bit internal addressing
•External access possible through selection of 8/16-bit bus width (external bus mode)
• Optimum instruction set for controller applications
•Wealth of data types (Bit, Byte, Word, Long Word)
•Wealth of addressing modes (23 different modes)
•Enhanced signed multiply-divide instructions and RETI instruction functions
•Enhanced high-precision arithmetic employing 32-bit accumulator
• Instruction set supports high-level programming language (C) and multitasking
•Employs system stack pointer
•Enhanced indirect instructions with all pointer types
•Barrel shift instructions
• Improved execution speed
•4-byte instruction queue
• Powerful interrupt feature
•Powerful 8-level, 34-condition interrupt feature
• CPU-independent automated data forwarding
•Extended intelligent I/O service feature (EI
2
OS) : maximum 16 channels
• Low-power consumption (Standby) Mode
•Sleep mode (CPU operation clock stopped)
•Time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational)
•Watch mode (subclock and watch timer only operational)
•Stop mode (oscillation clock and subclock stopped)
•CPU intermittent operation mode
• Process
•CMOS technology
• I/O Ports
•Generic I/O ports (CMOS output) : 49
• Timer
•Time-base timer, watch timer, watchdog timer : 1 channel
•8/16-bit PPG timer : four 8-bit channels, or two 16-bit channels
•16-bit reload timer : 2 channels
•16-bit I/O timer
•16-bit
free-run timer : 1 channel
•16-bit
input capture (ICU) : 4 channels
Generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input
edge detection
(Continued)
2
MB90495G Series
(Continued)
•
CAN Controller
:
1 channel
•CAN specifications conform to versions 2.0A and 2.0B
•8 on-chip message buffers
•Forwarding rate 10 Kbps to 1 Mbps (with 16-MHz machine clock)
• UART0 (SCI) /UART1 (SCI) : 2 channels
•All with full duplex double buffer
•Use clock-asynchronous or clock-synchronous serial forwarding
• DTP/external interrupt : 8 channels
•A module for launching extended intelligent I/O service (EI
2
OS) and generating external interrupts through
external output
• Delayed interrupt generation module
•Generates interrupt requests for switching tasks
• 8/10-bit A/D converter : 8 channels
•Switch between 8-bit and 10-bit resolution
•Launch through external trigger input
•Conversion time : 6.13
µs
(with 16-MHz machine clock, including sampling time)
• Program batch function
•2-address pointer ROM correction
• Clock output function
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MB90495G Series
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PRODUCT LINEUP
Part Number
Paarmeter
Feature Classification
ROM Size
RAM Size
Process
Package
Operating Power
Emulator power supply*
Number of instructions
Instruction bit length
Instruction length
Data bit length
: 351
: 8-bit, 16-bit
: 1 to 7 bytes
: 1 bit, 8-bit, 16-bit
MB90F497G
FLASH ROM
MB90497G
Mask ROM
2 Kbytes
CMOS
LQFP64 (width 0.65 mm) , QFP64 (width 1.0 mm)
4.5 V to 5.5 V
None
PGA256
MB90F498G
FLASH ROM
128 Kbytes
MB90V495G
Product Evaluated
6 Kbytes
64 Kbytes
CPU Functions
Minimum execution time : 62.5 ns (with 16-MHz machine clock)
Interrupt processing time : minimum 1.5
µs
(with 16-MHz machine clock)
Low-power consumption
(Standby) Mode
I/O Ports
Time-base timer
Sleep mode/watch mode/time-base timer mode/stop mode / CPU intermittent
mode
General-purpose I/O ports (CMOS output) : 49
18-bit free-run counter
Interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms
(with 4-MHz oscillation clock)
Reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(with 4-MHz oscillation clock)
16-bit
Number of channels : 1
free-run timer Interrupts from overflow generation
Input capture
Number of channels : 4
Maintenance of free-run timer value through pin input (rising, falling or both edg-
es)
Number of channels : 2
16-bit reload timer operation
Count clock interval : 0.25
µs,
0.5
µs,
2.0
µs
(with 16-MHz machine clock)
External event count enabled
15-bit free-run counter
Interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s
(with 8.192-kHz subclock)
Number of channels : 2 (two 8-bit channels can be used)
Two 8-bit or one 16-bit channel PPG operation possible
Free interval, free duty pulse output possible
Count clock : 62.5 ns to 1
µs
(with 16-MHz machine clock)
Watchdog timer
16-bit
I/O Timer
16-bit reload timer
Watch timer
8/16-bit PPG timer
* : The S2 dipswitch setting when using the MB2145-507 emulation baud. For details, see the MB2145-507
hardware manual (2.7 Emulator Power Pin) .
(Continued)
4
MB90495G Series
(Continued)
Part Number
Parameter
Delayed interrupt generation
module
DTP/external interrupt circuit
MB90F497G
MB90497G
MB90F498G
MB90V495G
Module for delayed interrupt generation switching tasks
Used in real-time OS
Number of inputs : 8
Starting by rising edge, falling edge, “H” level input, or “L” level input, external
interrupts or extended intelligent I/O service (EI
2
OS) can be used
Number of channels : 8
Resolution : set 10-bit or 8-bit
Conversion time : 6.13
µs
(with 16-MHz machine clock, including sampling time)
Continuous conversion of multiple linked channels possible
(up to 8 channels can be set)
One-shot conversion mode : converts selected channel only once
Continuous conversion mode : converts selected channel continuously
Stop conversion mode : converts selected channel and suspends operation
repeatedly
Number of channels : 1
Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps
Clock-asynchronous forwarding : 1,202 bps to 62,500 bps
Transmission can be performed by two-way serial transmission or by master/
slave connection
Number of channels : 1
Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps
Clock-asynchronous forwarding : 9,615 bps to 500 Kbps
Transmission can be performed by two-way serial transmission or by master/
slave connection
Compliant with CAN specification versions 2.0A and 2.0B
Send/receive message buffers : 8
Forwarding bit rate : 10 Kbps to 1 Mbps (with 16-MHz machine clock)
8/10-bit A/D converter
UART0 (SCI)
UART1 (SCI)
CAN
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PACKAGES AND CORRESPONDING PRODUCTS
Package
FPT-64P-M06
FPT-64P-M09
: available
×
: not available
Note : See “Package Dimensions” for details.
MB90F497G
MB90497G
MB90F498G
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PRODUCT COMPARISON
Memory Size
When evaluating with evaluation chips and other means, take careful note of the different between the evaluation
chip and the chip actually used. Take particular note of the following.
• While the MB90V495G does not feature an on-chip ROM, the dedicated development tool can be used to
achieve operation equivalent to a product with built-in ROM. Therefore, the ROM size is configured by the
development tool.
• On the MB90V495G, the FF4000
H
to FFFFFF
H
image is only visible in the 00 bank, and the FE0000
H
to
FF3FFF
H
is only visible in the FE and FF banks (configurable on development tool) .
• On the MB90F497G/F498G/497G, the FF4000
H
to FFFFFF
H
image is visible in the 00 bank, and the FF0000
H
to FF3FFF
H
is visible only in the FF bank.
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