FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13723-6E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90390 Series
MB90394HA/F394H/F394HA/
MB90V390H/V390HA/V390HB
■
DESCRIPTION
The MB90390-series with up to five FULL-CAN* interfaces and Flash ROM is especially designed for automotive
and industrial applications. Its main feature are up to five on board CAN Interfaces, which conform to V2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach. With the new 0.35
µm
CMOS technology, Fujitsu now offers on-chip Flash-ROM
program memory up to 512 Kbytes. An internal voltage booster removes the necessity for a second programming
voltage.
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features 6 Stepper Motor Controllers with slew rate controlled high current outputs.
Furthermore it features an 8-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate
16-bit free running timers. Up to 4 UARTs constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
MB90390 Series
■
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instruction execution time)
New 0.35
µm
CMOS Process Technology
Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures
Up to five FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, flexible message buffering
(mailbox and FIFO buffering can be mixed)
Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)
EI
2
OS - Automatic transfer function indep.of CPU; 16 channels of intelligent I/O Services
18-bit Time-base counter
Watchdog Timer
2 full duplex UARTs; support 10.4 Kbps (USA standard )
Up to 2 full duplex UARTs (LIN/SCI)
Serial I/O : 1 channel for synchronous data transfer
Optional I
2
C* with 400 Kbps
A/D Converter : 15 channels analog inputs (Resolution 10 bits or 8 bits)
16-bit reload timer
×
2 channels
ICU (Input capture) 16-bit
×
6 channels (2 input pins are shared with OCU outputs)
OCU (Output capture) 16-bit
×
8 channels (2 output pins are shared with ICU input pins)
16-bit free running timer
×
2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5, OCU 4/5/6/7)
8/16-bit Programmable Pulse Generator 6 channels
×
16-bit/12 channels
×
8-bit
Stepping Motor Controller 6 channels with slew rate controlled high current outputs
Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
4-byte instruction execution queue
signed multiply (16-bit
×
16-bit) and divide (32-bit/16-bit) instructions available
Program Patch Function
Fast Interrupt processing
Low Power Consumption mode
Sleep mode
Timebase timer mode
Stop mode
CPU intermittent mode
Sound Generator
Real Time Watch Timer
Built-In Clock Modulation circuit
Programmable input levels (Automotive Hysteresis / CMOS Hysteresis, initial level is Automotive Hysteresis)
Package : 120-pin plastic LQFP
•
•
•
•
•
* : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined
by Philips.
2
MB90390 Series
■
PRODUCT LINEUP
Part Number
Parameter
CPU
System clock
MB90394HA
MB90F394H
MB90F394HA
MB90V390H
MB90V390HA/
MB90V390HB
F
2
MC-16LX CPU
On-chip PLL clock multiplier (
×
1,
×
2,
×
3,
×
4,
×
6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL
×
6)
Boot-block
Flash memory 384
Kbytes
Hard-wired reset vector,
points to address
FFA000
H
16 Kbytes
Yes
ROM
ROM memory 384
Kbytes
External
RAM
Emulator-specific
power supply*
1
10 Kbytes
⎯
30 Kbytes
Technology
0.35
µm
CMOS with on-
chip
0.35
µm
CMOS with
voltage regulator for in-
on-chip
ternal power supply
+
0.35
µm
CMOS with on-chip
voltage regulator for
Flash memory with
voltage regulator for internal power supply
internal
On-chip charge pump
power supply
for
programming voltage
3.5 V to 5.5 V
(4.0 V to 5.5 V: during Flash programming
and erasing,
4.5 V to 5.5 V: if A/D Converter is used)
−40 °C
to
+85 °C
LQFP-120
5 V
±
10%
⎯
PGA-299
Operating
voltage range
Temperature range
Package
UART
(2 channels)
UART (LIN/SCI)
I
2
C (400 Kbps)
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock
=
24 MHz
1 channel
1 channel
⎯
1 channel
2 channels
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock
=
24 MHz
15 input channels
10-bit or 8-bit resolution
Conversion time : Min 4.9
µs
include sample time (per one channel, depends on machine
clock frequency)
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
=
System clock frequency)
Supports External Event Count function
(Continued)
3
A/D Converter
16-bit Reload Timer
(2 channels)
MB90390 Series
Part Number
Parameter
Watch Timer
MB90394HA
MB90F394H
MB90F394HA
MB90V390H
MB90V390HA/
MB90V390HB
Directly operates with the oscillation clock
Read/Write accessible Second/Minute/Hour registers
Signals interrupts
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
=
System clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5, OCU 4/5/6/7
Signals an interrupt when a match with 16-bit I/O Timer
Eight 16-bit compare registers.
A pair of compare registers can be used to generate an output signal.
OCU 6/7 outputs are shared with ICU 3/5 inputs
Rising edge, falling edge or rising & falling edge sensitive
Six 16-bit Capture registers
Signals an interrupt upon external event
ICU 3/5 inputs are shared with OCU 6/7 outputs
16-bit
I/O Timer
(2 channels)
16-bit
Output Compare
(8 channels)
16-bit
Input Capture
(6 channels)
Supports 8-bit and 16-bit operation modes
Twelve 8-bit reload counters
8/16-bit
Twelve 8-bit reload registers for L pulse width
Programmable Pulse Twelve 8-bit reload registers for H pulse width
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
(6 channels)
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
or 102.4
µs
at fosc
=
5 MHz
(fsys
=
System clock frequency, fosc
=
Oscillation clock frequency)
2 channels
5 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full-bit compare/Full-bit mask/Two partial bit masks
Supports up to 1 Mbps
MB90F394H, MB90V390H, MB90V390HA :
Do not use CAN message buffer RAM and clock modulator at the same time.
Four high current outputs with controlled slew rate for each channel
Synchronized two 8-bit PWM’s for each channel
Can be programmed edge sensitive or level sensitive
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz at System clock
=
16 MHz
Tone frequency : PWM frequency/2/ (reload value
+
1)
(Continued)
CAN Interface
(up to 5 channels)
Stepping Motor
Controller
(6 channels)
External Interrupt
(8 channels)
Sound Generator
4
MB90390 Series
(Continued)
Part Number
Parameter
MB90394HA
MB90F394H
MB90F394HA
MB90V390H
MB90V390HA/
MB90V390HB
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
Port-wise programmable as CMOS Hysteresis or automotive Hysteresis inputs (default)
Spread spectrum clock modulator for reducing electromagnetic emissions.
Frequency and Phase Modulation modes.
MB90F394H :
Do not use frequency modulation.
MB90F394H, MB90V390H, MB90V390HA :
Do not use CAN message buffer RAM and clock modulator at the same time.
Supports automatic
programming,
Embedded Algorith-
m
TM
*
2
Write/Erase/Erase-
Suspend/Resume
commands
A flag indicating com-
pletion of the algorithm
Number of erase cycles
: 10,000 times
Data retention time : 20
years*
3
Hard-wired reset vector
available in order to
point to a fixed boot
sector in Flash Memory
Boot block configura-
tion
Erase can be per-
formed on each block
Block protection with
external programming
voltage
Clock Modulator
Flash
Memory
⎯
⎯
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*3 : This value comes from the technology qualification (using Arrehenius equation to translate high temperature
measurements into normalized value at +85
°C)
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
