FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16702-2E
32
-
bit Proprietary Microcontroller
CMOS
FR60Lite
MB91265 Series
MB91266/MB91F267/MB91F267N
■
DESCRIPTION
The MB91265 series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications which
require high-speed processing.
The CPU is used the FR family and the compatibility of FR60Lite.
MB91F267N loads the C-CAN (1 channel) .
■
FEATURES
•
FR60Lite CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, barrel shift instructions, etc. : Instructions suitable for embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
(Continued)
■
PACKAGE
64-pin plastic LQFP
(FPT-64P-M23)
MB91265 Series
(Continued)
• Register interlock function : Facilitates coding in assembler.
• Built-in multiplier with instruction-level support
•
32-bit multiplication with sign : 5 cycles
•
16-bit multiplication with sign : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction compatible with FR family
•
Internal peripheral functions
• Capacity of internal ROM and ROM type
MASK ROM : 64 Kbytes (MB91266)
FLASH ROM : 128 Kbytes (MB91F267/MB91F267N)
• Capacity of internal RAM : 2 Kbytes (MASK product)/4 Kbytes (FLASH memory product)
• A/D converter (sequential comparison type)
Resolution : 8/10 bits : 4 channels
×
1 unit, 7 channels
×
1 unit
Conversion time : 1.2
µs
(Minimum conversion time system clock at 33 MHz)
1.35
µs
(Minimum conversion time system clock at 20 MHz)
• External interrupt input : 8 channels
• Bit search module (for REALOS)
Function for searching the MSB (upper bit) in each word for the first 1-to-0 inverted bit position
• C-CAN 32MSB : 1 channel (loaded in MB91F267N only)
• UART (Full-duplex double buffer) : 2 channels
Selectable parity On/Off
Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
Internal timer for dedicated baud rate (U-TIMER) on each channel
External clock can be used as transfer clock
Error detection function for parity, frame, and overrun errors
• 8/16-bit PPG timer : 8 channels (at 8-bit) / 4 channels (at 16-bit)
• Timing generator
• 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0)
• 16-bit free-run timer : 3 channels
• 16-bit PWC timer : 1 channel
• Input capture : 4 channels (interface with free-run timer)
• Output compare : 6 channels (interface with free-run timer)
• Waveform generator
Various waveforms which are generated by using output compare, 16-bit PPG timer 0, and 16-bit dead timer
• SUM of products macro
RAM : instruction RAM (I-RAM) 256
×
16-bit
coefficient RAM (X-RAM) 64
×
16-bit
variable RAM (Y-RAM)
64
×
16-bit
Execution of 1 cycle MAC (16-bit
×
16-bit + 40 bits)
Operation results are extracted rounded from 40 to 16 bits
• DMAC (DMA Controller) : 5 channels
Operation of transfer and activation by internal peripheral interrupts and software
• Watchdog timer
• Low-power consumption mode
Sleep/stop function
• Package : LQFP-64P
• Technology : CMOS 0.35
µm
• Power supply : 1-power supply (Vcc
=
4.0 V to 5.5 V)
2
MB91265 Series
■
PIN ASSIGNMENT
(TOP VIEW)
AV
CC
AVRH2
AVRH1
P43/INT3
P42/INT2
P41/INT1
P40/INT0
P30/RTO0
P31/RTO1
P32/RTO2
P33/RTO3
P34/RTO4
P35/RTO5
INIT
P36/PPG7/INT7
P37/PPG4
AV
SS
ACC
AN0/P50
AN1/P51
AN2/P52
AN3/P53
AN4/P54
AN5/P55
AN6/P56
AN7/P57
AN8/P44
AN9/P45
AN10/P46
NMI
C
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
SS
X1
X0
MD0
MD1
MD2
PG1/PPG0
P27
P26/IC1
P25/IC0
P24/CKI
P23/DTTI
P22/PWI0
P21/ADTG2/IC3
P20/ADTG1/IC2
P17/PPG6/TX0*
* : C-CAN pin is loaded in only MB91F267N.
V
CC
P00/PPG1/INT4
P01/PPG2
P02/PPG3/INT5
P03/TIN0
P04/TIN1
P05/TIN2
P06/TOT1
P07/TOT2
P10/SOT0
P11/SIN0
P12/SCK0
P13/SOT1
P14/SIN1
P15/SCK1
P16/PPG5/INT6/RX0*
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
(FPT-64P-M23)
3
MB91265 Series
■
PIN DESCRIPTION
Pin no.
Pin Circuit
name type
AN0
3
P50
AN1
4
P51
AN2
5
P52
AN3
6
P53
AN4
7
P54
AN5
8
P55
AN6
9
P56
AN7
10
P57
AN8
11
P44
AN9
12
P45
G
G
G
G
G
G
G
G
G
G
Description
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
(Continued)
4
MB91265 Series
Pin no.
Pin Circuit
name type
AN10
13
P46
14
NMI
INT4
18
PPG1
P00
PPG2
19
P01
INT5
20
PPG3
P02
E
D
E
H
G
Description
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog
input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
NMI (Non Maskable Interrupt) input terminal.
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
Output terminal of PPG timer 1.
This function becomes valid when output of PPG timer 1 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 1 and external interrupt input
are set to disabled.
Output terminal of PPG timer 2.
This function becomes valid when output of PPG timer 2 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 2 is set to disabled.
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
Output terminal of PPG timer 3.
This function becomes valid when output of PPG timer 3 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 3 and external interrupt input
are set to disabled.
External trigger input terminal of reload timer 0.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
General purpose input/output port.
This function becomes valid when external clock input of reload timer 0 is set to
disabled.
External trigger input terminal of reload timer 1.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
General purpose input/output port.
This function becomes valid when external clock input of reload timer 1 is set to
disabled.
External trigger input terminal of reload timer 2.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
General purpose input/output port.
This function becomes valid when external clock input of reload timer 2 is set to
disabled.
(Continued)
5
TIN0
21
P03
D
TIN1
22
P04
D
TIN2
23
P05
D
FPGA/CPLD
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