FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12611-1E
8-bit Proprietary Microcontrollers
CMOS
F MC-8FX MB95110M series
MB95117M/F114MS/F114NS/F116MS/F116NS/
MB95F118MS/F118NS/F114MW/F114NW/F116MW/F116NW/
MB95F118MW/F118NW/FV100D-103
■
DESCRIPTION
The MB95110M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
2
■
FEATURES
•
F
2
MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
•
Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
•
Timer
• 8/16-bit compound timer
×
2 channels
• 8/16-bit PPG
×
2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB95110M Series
(Continued)
•
LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
•
UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
2
C*
•
I
Built-in wake-up function
•
External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
•
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
•
Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
•
I/O port
• The number of maximum ports
•
Single clock product : 39 ports
•
Dual clock product : 37 ports
• Configuration
•
General-purpose I/O ports (N-ch open drain) : 2 ports
•
General-purpose I/O ports (CMOS)
: Single clock product : 37 ports
Dual clock product : 35 ports
•
Programmable input voltage levels of port
Automotive input level
/
CMOS input level
/
hysteresis input level
•
Flash memory security function
Protects the content of Flash memory (Flash memory device only)
* : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these com-
ponents in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined by
Philips.
2
MB95110M Series
■
MEMORY LINEUP
Flash memory
MB95F114MS/F114NS
MB95F114MW/F114NW
MB95F116MS/F116NS
MB95F116MW/F116NW
MB95F118MS/F118NS
MB95F118MW/F118NW
16 Kbytes
32 Kbytes
60 Kbytes
RAM
512 bytes
1 Kbyte
2 Kbytes
3
MB95110M Series
■
PRODUCT LINEUP
Part number
MB95117M
Parameter
Type
ROM capacity*
1
RAM capacity*
1
Reset output
Option*
2
Clock system
Low voltage
detection reset
Selectable single/
dual clock*
3
Yes / No
No
:
:
:
:
:
:
MASK ROM product
48 Kbytes
2 Kbytes
Yes
Single clock
Yes
No
Dual clock
Yes
MB95F114MS MB95F114NS MB95F114MW MB95F114NW
MB95F116MS MB95F116NS MB95F116MW MB95F116NW
MB95F118MS MB95F118NS MB95F118MW MB95F118NW
Flash memory product
60 Kbytes (Max)
2 Kbytes
(
Max
)
CPU functions
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
136
8 bits
1 to 3 bytes
1, 8, and 16 bits
61.5 ns (at machine clock frequency 16.25 MHz)
0.6
µs
(at machine clock frequency 16.25 MHz)
•
Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
General purpose I/O
•
Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports)
ports
Programmable input voltage levels of port :
Automotive input level
/
CMOS input level
/
hysteresis input level
Timebase timer
Peripheral functions
Watchdog timer
Wild register
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate
generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
(Continued)
I
2
C
UART/SIO
4
MB95110M Series
(Continued)
Part number
MB95117M
Parameter
MB95F114MS MB95F114NS MB95F114MW MB95F114NW
MB95F116MS MB95F116NS MB95F116MW MB95F116NW
MB95F118MS MB95F118NS MB95F118MW MB95F118NW
LIN-UART
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer
capable.
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(8 channels)
Each channel of the timer can be used as “8-bit timer
×
2 channels” or “16-bit timer
×
1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
waveform output
Count clock : 7 internal clocks and external clock can be selected
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
Each channel of the PPG can be used as
“
8-bit PPG
×
2 channels
”
or
“
16-bit PPG
×
1 channel
”
.
Counter operating clock : Eight selectable clock sources
Peripheral functions
8/16-bit compound
timer (2 channels)
16-bit PPG
8/16-bit PPG
(2 channels)
Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Watch counter
Counter value can be set from 0 to 63. (Capable of counting for 1minute when
(for dual clock product)
selecting clock source 1 second and setting counter value to 60)
Watch prescaler
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
(for dual clock product)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Supports automatic programming, Embedded Algorithm
TM
*
4
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Sleep, stop, watch (for dual clock product) , and timebase timer
Flash memory
Standby mode
*1 : For ROM capacity and RAM capacity, refer to “1. Memory space” in “■ CPU CORE”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of the evaluation device in MB95110M series is MB95FV100D-103. When using it, the MCU
board (MB2146-303A) is required.
5
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