FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12616-1E
8-bit Proprietary Microcontrollers
CMOS
F MC-8FX MB95120 series
MB95F128D/F128E/FV100D-101/FV100D-102
■
DESCRIPTION
The MB95120 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
2
■
FEATURE
•
F
2
MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
•
Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
•
Timer
• 8/16-bit compound timer
×
2 channels
• 16-bit reload timer
• 8/16-bit PPG
×
2 channels
• 16-bit PPG
×
2 channels
• Timebase timer
• Watch prescaler
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB95120 Series
(Continued)
•
LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
•
UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
2
C*
•
I
• Built-in wake-up function
•
External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
•
8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected
•
LCD controller (LCDC)
• 40 SEG
×
4 COM (Max 160 pixels)
• With blinking function
• Built-in division resistance for LCD drive/booster : selected by mask option
•
Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
•
I/O port
• The number of maximum ports : Max 87
• Port configuration
•
General-purpose I/O ports (N-ch open drain) : 2 ports
•
General-purpose I/O ports (CMOS)
: 85 ports
•
Programmable input voltage levels of port
• CMOS input level / hysteresis input level
•
Dual operation Flash memory
• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
•
Flash memory security function
Protects the content of Flash memory (Flash memory product only)
*:
Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined
by Philips.
2
MB95120 Series
■
PRODUCT LINEUP
Part number*
1
MB95F128D
Parameter
Type
ROM capacity
RAM capacity
Reset output
Option*
2
Clock system
Low voltage
detection reset
Flash memory product
60 Kbytes
2 Kbytes
No
Dual clock
No
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6
µs
(at machine clock frequency 16.25 MHz)
General-purpose I/O port (N-ch open drain)
General-purpose I/O port (CMOS)
Programmable input voltage levels of port
CMOS input level / hysteresis input level
Reset generated cycle
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
Data transfer capable in UART/SIO
Full duplex double buffer
Variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set
Full duplex double buffer
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave
: 2 ports
: 85 ports
MB95F128E
CPU functions
Ports (Max 87 ports)
Timebase timer
Watchdog timer
Wild register
Peripheral functions
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
: Min 105 ms
: Min 250 ms
I
2
C
UART/SIO
LIN-UART
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
(12 channels)
(Continued)
3
MB95120 Series
(Continued)
Part number*
1
MB95F128D
Parameter
COM output
: 4 (Max)
SEG output
: 40 (Max)
LCD drive power supply (bias) pin
:4
40 SEG
×
4 COM
: 160 pixels can be displayed
Duty LCD mode
With blinking function
Division resistance for LCD drive/booster : selected by mask option
Built-in internal division resistance :
selected by mask option
16-bit reload timer
Peripheral functions
Built-in booster circuit :
selected by mask option
MB95F128E
LCD controller
(LCDC)
Two clock modes and two counter operating modes can be selected
Square wave form output
Count clock : 7 internal clocks and external clock can be selected
Counter operating mode : reload mode or one-shot mode can be selected
Each channel of the timer can be used as “8-bit timer
×
2 channels” or “16-bit timer
×
1 channel”
8/16-bit compound
Built-in timer function, PWC function, PWM function, capture function and square
timer (2 channels)
wave form output
Count clock : 7 internal clocks and external clock can be selected
16-bit PPG
(2 channels)
8/16-bit PPG
(2 channels)
Watch counter
Watch prescaler
External interrupt
(12 channels)
PWM mode or one-shot mode can be selected
Counter operating clock : Eight selectable clock sources
Support for external trigger start
Each channel of the PPG can be used as
“
8-bit PPG
×
2 channels
”
or
“
16-bit PPG
×
1 channel
”
Counter operating clock : Eight selectable clock sources
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63 (Capable of counting for 1 minute when selecting
clock source 1 second and setting counter value to 60)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
Interrupt by edge detection (rising, falling, or both edges can be selected)
Can be used to recover from standby modes
Supports automatic programming, Embedded Algorithm
TM
*
3
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Dual operation Flash memory
Flash Security Feature for protecting the content of the Flash
Sleep, stop, watch, and timebase timer
Flash memory
Standby mode
*1 : MASK ROM products are currently under consideration.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of evaluation product in MB95120 series is MB95FV100D-101 (internal division resistance
included) or MB95FV100D-102 (LCD booster circuit included) . When using it, the MCU board (MB2146-
301A or MB2146-302A) is required.
4
MB95120 Series
■
OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
(2
14
−2)
/F
CH
Remarks
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■
PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
FPT-100P-M20
FPT-100P-M06
BGA-224P-M08
: Available
: Unavailable
MB95F128D/F128E
MB95FV100D-101/102
5
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