FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16307-3E
32-Bit RISC Microcontroller
CMOS
FR Family MB91110 Series
MB91110/MB91V110
s
DESCRIPTION
The MB91110 series is a standard single-chip micro controller featuring various I/O resources and bus control
mechanisms to incorporate the control with required for high performance high-speed CPU processes, having a
32-bit RISC CPU (FR30 series) in its core. Although external bus access is the basis for supporting a large address
space accessible by a 32-bit CPU, a 1-KB instruction cache memory has been built-in to increase the instruction/
execution speed of the CPU.
This unit features the optimal specifications for incorporating applications that require high performance CPU
processing power such as navigation systems, high performance facsimile systems, printer control, etc.
s
FEATURES
FR30CPU
• 32-bit RISC, load / store architecture, 5-level pipeline
• Operating frequency : external 25 MHz, internal 50 MHz
• Multi-purpose register : 32 bits
×
16
• 16-bit fixed length instructions (basic instruction) , 1 instruction per cycle
• Instructions for barrel shift, bit processing and inter memory transfers : Instructions suited to loading purposes
(Continued)
s
PACKAGE
144-pin plastic LQFP
(FPT-144P-M08)
MB91110 Series
(Continued)
• Function entry / exit instruction, multi load / store instruction of register details : Instruction capable of handling
High level language instruction.
• Register Interlock function : Simplification of assembler description
• Branch instruction with delay slot : Reduction in overheads in case of branching
• Multiplier is built-in / Supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interruption (saving PC and PS) : 6 cycles, 16 priority levels
Bus Interface
• 24-bit address bus (16 MB space)
• Operating frequency : 25 MHz
• 16- / 8-bit data bus
• Basic external bus cycle : 2 clock cycles
• Chip select output that can be set to a minimum 64-Kbyte units
• Interface support for various memories
DRAM interface (areas 4, 5)
• Automatic waiting cycle : Can be randomly set from 0 to 7 cycles per area
• Unused data and address pins can be used as input/output ports.
• Supports “little endian” mode (One area is selected from areas 1 to 5)
DRAM Interface
• 2-bank individual control (area 4, 5)
• Normal mode / high speed page mode
• Basic bus cycles : normally 5 cycles, 1 cycle access is possible in high-speed page mode.
• Programmable waveform : 1 cycle waiting can be inserted automatically in RAS and CAS.
• DRAM refresh
CBR refresh (Interval is randomly set using the 6-bit timer.)
Self refresh mode
• Supports addresses for 8, 9, 10 and 12 columns
• 2CAS/1WE or 2WE/1CAS can be selected.
Cache Memory
• 1 KB instruction cache
• 2 way set associative
• 32 blocks / way, 4 entries (4 words) / block
• Lock function : Residing in the specified program codes at cache
DMA Controller
(DMAC)
• 5 channels
• External
→
external 2.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)
• Internal
→
external 1.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)
• Address register (inc, dec, or reload are possible) : 32 bits
×
5 channels
• Transfer count register (reload possible) : 16 bits
×
5 channels
• Transfer factors : external pin / built-in resources interruption request / software
• Transfer sequence
Step transfer / block transfer
Burst / consecutive transfer
• Transfer data length : 8-bit, 16-bit or 32-bit can be selected
• Suspension is possible using NMI / interruption request
2
MB91110 Series
UART
• Fully duplicated double buffer
• Data length : 7 to 9 bits (without parity) , 6 to 8 bits (with parity)
• Asynchronous (start-stop synchronization) or CLK synchronized communication can be selected.
• Multiprocessor mode
• Dedicated baud rate generator is built-in.
• External clock can be used as the transfer clock
• Baud rate clock can be output
• Error detection : parity, frame, overrun
PPG Timer
• 16 bits, 6 channels (frequency setting register / duty setting register)
• PWM function or one-shot function can be selected
• Initiation : Software or external trigger can be selected
A/D Converter
(sequential
conversion type)
• 10-bit resolution, 8 channels
• Sequential comparison conversion : 5.6
µs
in the case of 25 MHz
• Sample & hold circuit is built-in.
• Conversion mode : Single, scan or repeat conversion can be selected.
• Initiation : Software, external trigger or built-in timer can be selected.
Reloading Timer
• 16-bit timer : 2 channels
• Internal clock : 2 clock cycle resolutions, 2, 8 or 32 cycles can be selected.
• Pin input : event counter input / gate function
• Rectangular wave output
Other Interval Timer
• Watchdog timer : 1 channel
Bit Search Module
• Searches the first “1” / “0” change bit positions within 1 cycle from MSB in 1 word.
Interruption Controller
• External interruption input : Mask impossible interruption (NMI) , normal interruption
×
8 (INT0 to INT7)
• Internal interruption factors : UART, DMAC, A/D, reloading timer, PPG timer, delay interruption
• Priority levels are programmable except for mask impossible interruption (16 levels)
Reset Factors
• Power-on reset / hardware standby / watchdog timer / software reset / external reset
Low Power Consumption Mode
• Sleep / stop mode
Clock Control
• Gear functions : Operating clock frequencies peripheral to the CPU can be set randomly and independently.
Gear locks can be selected from 1/1, 1/2, 1/4 or 1/8 (or 1/2, 1/4, 1/8, or 1/16) .
Others
• Package : LQFP-144
• CMOS technology : 0.35
µm
• Power : 5.0 V
±
10%, 3.3 V
±
5%
3
MB91110 Series
s
PRODUCT LINEUP
MB91V110
(For evaluation)
I-RAM
RAM
ROM
I-$
DSU3
evaluation function
16 Kbyte
5 Kbyte
1 Kbyte
Mounted
MB91110
(I-RAM mounted version)
16 Kbyte
5 Kbyte
1 Kbyte
4
MB91110 Series
s
PIN ASSIGNMENT
(TOP VIEW)
TRG1, 4/PE2
TRG0, 3/PE1
ATG/PE0
V
SS
V
CC
5
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AV
SS
AVRL
AVRH
AV
CC
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
V
CC
3
HST
RST
V
SS
X1
X0
V
CC
5
MD2
MD1
MD0
105
100
95
90
85
80
PE3/TRG2, 5
PF0/INT0
PF1/INT1
PF2/INT2
PF3/INT3
PF4/INT4
PF5/INT5
PF6/INT6
PF7/INT7
V
SS
PG0/DREQ0
PG1/DACK0
PG2/DEOP0
PG3/DREQ1
PG4/DACK1
PG5/DEOP1
V
CC
5
V
CC
3
PH0/DREQ2
PH1/DACK2
PH2/DEOP2
PH3/SI
PH4/SO
PH5/SCK
PH6/TI0
PH7/TO0
V
SS
PI0/TI1
PI1/TO1
PI2/PPG0
PI3/PPG1
PI4/PPG2
PI5/PPG3
PI6/PPG4
PI7/PPG5
V
SS
75
110
70
115
65
120
60
125
55
130
50
135
45
140
INDEX
40
10
15
20
25
30
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
V
SS
D24
D25
D26
D27
D28
D29
D30
D31
V
CC
5
V
SS
A00
A01
A02
A03
A04
A05
A06
A07
V
SS
A08
A09
A10
A11
A12
A13
A14
A15
(FPT-144P-M08)
35
NMI
DW1/PB7
CS1H/PB6
CS1L/PB5
RAS1/PB4
V
SS
V
CC
5
DW0/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3
CS2/PA2
CS1/PA1
CS0
V
SS
WR1/P85
WR0
RD
BRQ/P82
BGRNT/P81
RDY/P80
V
CC
3
V
CC
5
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
V
SS
1
5
5
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
