TRC103
Product Overview
TRC103 is a single chip, multi-channel, low power UHF transceiver. It is
designed for low cost, high volume, two-way short range wireless applica-
tions in the 863-870, 902-928 and 950-960 MHz frequency bands. The
TRC103 is FCC & ETSI certifiable. All critical RF and base-band functions
are integrated in the TRC103, minimizing external component count and sim-
plifying and speeding design-ins. A microcontroller, RF SAW filter, 12.8 MHz
crystal and a few passive components are all that is needed to create a com-
plete, robust radio function. The TRC103 incorporates a set of low-power
states to reduce overall current consumption and extend battery life. The
small size and low power consumption of the TRC103 make it ideal for a
wide variety of short range radio applications. The TRC103 complies with
Directive 2002/95/EC (RoHS).
863-960 MHz
RF Transceiver
Pb
Key Features
Modulation: FSK or OOK with frequency hop-
ping and DTS spread spectrum capability
Frequency ranges: 863-870, 902-928 and
950-960 MHz
High sensitivity: -112 dBm in circuit
High data rate: up to 200 kb/s
Low receiver current: 3.3 mA typical
Low sleep current: 0.1 µA typical
Up to +11 dBm in-circuit transmit power
Operating supply voltage: 2.1 to 3.6 V
Programmable preamble
Programmable packet start pattern
Integrated RF, PLL, IF and base-band circuitry
Integrated data & clock recovery
Programmable RF output power
PLL lock output
Transmit/receive FIFO size programmable up
to 64 bytes
Continuous, Buffered and Packet data modes
Packet address recognition
Packet handling features:
Fixed or variable packet length
Packet filtering
Packet formatting
Standard SPI interface
TTL/CMOS compatible I/O pins
Programmable clock output frequency
Low cost 12.8 MHz crystal reference
Integrated RSSI
Integrated crystal oscillator
Host processor interrupt pins
Programmable data rate
External wake-up event inputs
Integrated packet CRC error detection
Integrated DC-balanced data scrambling
Integrated Manchester encoding/decoding
Interrupt signal mapping function
Support for multiple channels
Four power-saving modes
Low external component count
Small 32-pin QFN plastic package
Standard 13 inch reel, 3K pieces
Applications
Active RFID tags
Automated meter reading
Home & industrial automation
Security systems
Two-way remote keyless entry
Automobile immobilizers
Sports performance monitoring
Wireless toys
Medical equipment
Low power two-way telemetry systems
Wireless mesh sensor networks
Wireless modules
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E-mail:
info@rfm.com
© 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 1 of 65
TRC103 - 11/29/12
Table of Contents
1.0 Pin Configuration .....................................................................................................................................4
1.1 Pin Description ..................................................................................................................................4
2.0 Functional Description .............................................................................................................................5
2.1 RF Port ..............................................................................................................................................7
2.2 Transmitter ........................................................................................................................................7
2.3 Receiver ............................................................................................................................................8
2.4 Crystal Oscillator ...............................................................................................................................9
2.5 Frequency Synthesizer ...................................................................................................................10
2.6 PLL Loop Filter ................................................................................................................................10
3.0 Operating Modes ...................................................................................................................................11
3.1 Receiving in Continuous Mode .......................................................................................................12
3.2 Continuous Mode Data and Clock Recovery ..................................................................................13
3.3 Continuous Mode Start Pattern Recognition ..................................................................................14
3.4 RSSI ................................................................................................................................................14
3.5 Receiving in Buffered Data Mode ...................................................................................................15
3.6 Transmitting in Continuous or Buffered Data Modes ......................................................................17
3.7 IRQ0 and IRQ1 Mapping.................................................................................................................17
3.8 Buffered Clock Output .....................................................................................................................19
3.9 Packet Data Modes .........................................................................................................................19
3.9.1 Fixed Length Packet Mode ....................................................................................................19
3.9.2 Variable Length Packet Mode ...............................................................................................20
3.9.3 Extended Variable Length Packet Mode ...............................................................................20
3.9.4 Packet Payload Processing in Transmit and Receive ...........................................................22
3.9.5 Packet Filtering ......................................................................................................................23
3.9.6 Cyclic Redundancy Check.....................................................................................................23
3.9.7 Manchester Encoding ............................................................................................................24
3.9.8 DC-Balanced Scrambling ......................................................................................................24
3.10 SPI Configuration Interface ...........................................................................................................25
3.11 SPI Data FIFO Interface ...............................................................................................................27
4.0 Configuration Register Memory Map .....................................................................................................28
4.1 Main Configuration Registers (MCFG)............................................................................................29
4.2 Interrupt Configuration Registers (IRQCFG)...................................................................................32
4.3 Receiver Configuration Registers (RXCFG) ...................................................................................34
4.4 Start Pattern Configuration Registers (SYNCFG) ...........................................................................37
4.5 Transmitter Configuration Registers (TXCFG)................................................................................37
4.6 Oscillator Configuration Register (OSCFG) ....................................................................................38
4.7 Packet Handler Configuration Registers (PKTCFG) .......................................................................38
4.8 Page Configuration Register (PGCFG)...........................................................................................39
5.0 Electrical Characteristics .......................................................................................................................40
5.1 DC Electrical Characteristics ..........................................................................................................40
5.2 AC Electrical Characteristics ...........................................................................................................41
6.0 TRC103 Design-in Steps .......................................................................................................................43
6.1 Determining Frequency Specific Hardware Component Values ....................................................43
6.1.1 SAW Filters and Related Component Values .......................................................................43
6.1.2 Voltage Controlled Oscillator Component Values .................................................................43
6.2 Determining Configuration Values for FSK Modulation ..................................................................44
6.2.1 Bit Rate Related FSK Configuration Values ..........................................................................44
6.2.2 Determining Transmitter Power Configuration Values ..........................................................46
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Page 2 of 65
TRC103 - 11/29/12
6.3 Determining Configuration Values for OOK Modulation ........................................................................47
6.3.1 Bit Rate Related OOK Configuration Values ........................................................................47
6.3.2 OOK Demodulator Related Configuration Values .................................................................49
6.3.3 OOK Transmitter Related Configuration Values ...................................................................50
6.4 Frequency Synthesizer Channel Programming for FSK Modulation ..............................................51
6.5 Frequency Synthesizer Channel Programming for OOK Modulation .............................................52
6.6 TRC103 Data Mode Selection and Configuration ...........................................................................53
6.6.1 Continuous Data Mode ..........................................................................................................53
6.6.2 Buffered Data Mode ..............................................................................................................55
6.6.3 Packet Data Mode .................................................................................................................57
6.7 Battery Power Management Configuration Values .........................................................................61
7.0 Package Dimensions and Typical PCB Footprint - QFN-32 .................................................................63
8.0 Tape and Reel Dimensions ...................................................................................................................64
9.0 Solder Reflow Profile .............................................................................................................................65
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© 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 3 of 65
TRC103 - 11/29/12
1.0 Pin Configuration
V D D _ A N A
2 7
V D D _ D IG
V D D _ P A
G N D
R F +
G N D
G N D
2
3
4
5
6
7
8
V D D _ V C O
T A N K -
T A N K +
P L L -
P L L +
G N D
1
3 2
R F -
3 1
3 0
2 9
2 8
2 6
G N D
2 5
2 4
2 3
2 2
G N D
P L L _ L O C K
IR Q 1
IR Q 0
D A T A
C L K O U T
S C K
S D I
2 1
2 0
1 9
1 8
1 7
1 6
G N D P A D
O N B O T T O M
O F P A C K A G E
9
1 0
1 1
1 2
1 3
1 4
X T A L -
X T A L +
G N D
n S S _ C O N F IG
n S S _ D A T A
G N D
N C
V D D
1 5
1.1 Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PAD
TYPE
-
-
O
I/O
I/O
I/O
I/O
-
-
I
I
-
-
I
I
O
I
I
O
I/O
O
O
O
-
-
I
O
O
O
-
I/O
I/O
-
NAME
GND
GND
VDD_VCO
TANK-
TANK+
PLL-
PLL+
GND
GND
XTAL-
XTAL+
GND
NC
nSS_CONFIG
nSS_DATA
SDO
SDI
SCK
CLKOUT
DATA
IRQ0
IRQ1/DCLK
PLL_LOCK
GND
GND
VDD
VDD_ANALOG
VDD_DIG
VDD_PA
GND
RF-
RF+
GROUND
DESCRIPTION
CONNECT TO GND
CONNECT TO GND
REGULATED SUPPLY FOR VCO
VCO TANK
VCO TANK
PLL LOOP FILTER OUTPUT
PLL LOOP FILTER INPUT
CONNECT TO GND
CONNECT TO GND
CRYSTAL CONNECTION (OSCILLATOR OUTPUT)
CRYSTAL CONNECTION (OSCILLATOR INPUT)
CONNECT TO GND
NO CONNECT - FLOAT IN NORMAL OPERATION
SLAVE SELECT FOR SPI CONFIGURATION DATA
SLAVE SELECT FOR SPI TX/RX DATA
SERIAL DATA OUT
SERIAL DATA IN
SERIAL SPI CLOCK IN
BUFFERED CLOCK OUTPUT
TRANSMIT/RECEIVE DATA
INTERRUPT OUTPUT
INTERRUPT OUTPUT/RECOVERED DATA CLOCK (CONT MODE)
PLL LOCKED INDICATOR
CONNECT TO GND
CONNECT TO GND
MAIN 3.3 V SUPPLY VOLTAGE
REGULATED SUPPLY FOR ANALOG CIRCUITRY
REGULATED SUPPLY FOR DIGITAL CIRCUITRY
REGULATED SUPPLY FOR RF POWER AMP
CONNECT TO GND
RF I/O
RF I/O
GROUND PAD ON PKG BOTTOM
Table 1
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E-mail:
info@rfm.com
© 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 4 of 65
TRC103 - 11/29/12
S D O
2.0 Functional Description
The TRC103 is a single-chip transceiver that can operate in the 863-870 and 902-928 MHz license-free bands,
and in the 950-960 MHz RFID band. The TRC103 supports two modulation schemes - FSK and OOK. The
TRC103’s highly integrated architecture requires a minimum of external components, while maintaining design
flexibility. All major RF communication parameters are programmable and most can be dynamically set. The
TRC103 is optimized for very low power consumption (3.3 mA typical in receiver mode). It complies with Europe-
an ETSI, FCC Part 15 and Canadian RSS-210 regulatory standards. Advanced digital features including the
TX/RX FIFO and the packet handling data mode significantly reduce the load on the host microcontroller.
T R C 1 0 3 B lo c k D ia g r a m
T X L O 1 -I
+
T X L O 2 -I
O O K
M o d u la tio n
In p u t
-
T X L O 2 -Q
A n ti-
a lia s in g
F ilte r
+
D r iv e r
-
A n ti-
a lia s in g
F ilte r
+
T X L O 2 -I
D A C
T r a n s m it
W a v e fo rm
G e n e ra to r
D A C
R F +
R F -
P o w e r
A m p
+
T X L O 1 -Q
T X L O 2 -Q
R S S I
O O K
D e te c to r
S C K
S D I
D a ta &
C lo c k
R e c o v e ry
S D O
n S S _ D A T A
C o n tro l
n S S _ C O N F IG
D A T A
IR Q 1 /D C L K
IR Q 0
P L L _ L O C K
R X L O 2 -I
R -C
L o w -p a s s
F ilte r
L N A
R e c e iv e r
B a n d -p a s s
F ilte r
R X L O 1
V G A
R -C
L o w -p a s s
F ilte r
R X L O 2 -Q
B u tte rw o rth
o r
P o ly p h a s e
F ilte r
B u tte rw o rth
o r
P o ly p h a s e
F ilte r
IF A m p lifie r
L im ite r
F S K
D e te c to r
IF A m p lifie r
L im ite r
C L K O U T
O s c illa to r
D iv id e r &
B u ffe r
V C O
F re q u e n c y
D iv id e r
D iv id e
b y 8
T X L O 2 -I
T X L O 2 -Q
T X L O 1 -I
C ry s ta l
O s c illa to r
R e fe re n c e
F re q u e n c y
D iv id e r
C h a rg e
P u m p
P h a s e
D e te c to r
P L L
L o o p
F ilte r
V C O
I & Q
P h a s e
T X L O 1 -Q
R X L O 1
R X L O 2 -I
R X L O 2 -Q
F IF O
D iv id e
b y 8
X T A L +
P L L +
V C O +
The receiver is based on a superheterodyne architecture. It is composed of the following major blocks:
An LNA that provides low noise RF gain followed by an RF band-pass filter.
A first mixer which down-converts the RF signal to an intermediate frequency equal to 1/9 th of the carrier
frequency (about 100 MHz for 915 MHz signals).
A variable gain first IF preamplifier followed by two second mixers which down convert the first IF signal to
I and Q signals at a low frequency (zero-IF for FSK, low-IF for OOK).
www.RFM.com
E-mail:
info@rfm.com
© 2009-2010 by RF Monolithics, Inc.
X T A L -
Figure 1
Technical support +1.800.704.6079
P L L -
V C O -
Page 5 of 65
TRC103 - 11/29/12
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