- Compatible with Network Processor Streaming Interface (NPSI)
NPE-Framer mode of operation
- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over
the entire frequency range
- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle
- IEEE 1149.1 JTAG
- Serial or parallel microprocessor interface for control and monitoring
•
Full Suite of Performance Monitoring Counters
-
Number of packets
-
Number of fragments
•
-
Number of errors
-
Number of bytes
Green parts available, see ordering information
APPLICATIONS
•
•
•
•
•
Ethernet transport
SONET / SDH packet transport line cards
Broadband aggregation
Multi-service switches
IP services equipment
DESCRIPTION
The IDT88P8341 is a SPI (System Packet Interface) Exchange with a SPI-
3 interface and a SPI-4 interface. The data that enter on the low speed interface
(SPI-3) are mapped to logical identifiers (LIDs) and enqueued for transmission
over the high speed interface (SPI-4). The data that enter on the high speed
interface (SPI-4) are mapped to logical identifiers (LIDs) and enqueued for
transmission over the low speed interface (SPI-3). A data flow between SPI-
3 and SPI-4 interfaces is accomplished with LID maps. The logical port
addresses and number of entries in the LID maps may be dynamically
configured. Various parameters of a data flow may be configured by the user
such as buffer memory size and watermarks. In a typical application, the
IDT88P8341 enables connection of a SPI-3 device to a SPI-4 network
processor. In other applications a SPI-4 device may be connected to a SPI-3
network processor or traffic manager.
FUNCTIONAL BLOCK DIAGRAM
SPI-3 to SPI-4 PFP
SPI-3
64 Logical Ports
SPI-4 to SPI-3 PFP
SPI-4
64 Logical
Ports
JTAG IF
Uproc IF
Clock Generator
Control Path
Data Path
PFP = Packet Fragment Processor
6372 drw01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
1
2006
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
APRIL 2006
DSC-6372/9
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
Table of Contents
Features ........................................................................................................................................................................................................................ 1
4. Datapath and flow control .................................................................................................................................................................................... 23
4.1 SPI-3 to SPI-4 datapath and flow control .......................................................................................................................................................... 25
4.2 SPI-4 to SPI-3 datapath and flow control .......................................................................................................................................................... 30
4.3 Microprocessor interface to SPI-3 datapath ...................................................................................................................................................... 33
4.3.1 SPI-3 to ingress microprocessor interface datapath ................................................................................................................................ 33
4.3.2 Microprocessor insert to SPI-3 egress datapath ..................................................................................................................................... 34
4.3.3 Microprocessor interface to SPI-4 egress datapath ................................................................................................................................ 35
4.3.4 SPI-4 ingress to microprocessor interface datapath ................................................................................................................................ 36
5. Performance monitor and diagnostics ................................................................................................................................................................. 37
5.1 Mode of operation ............................................................................................................................................................................................ 37
5.2.1 LID associated event counters ............................................................................................................................................................... 37
5.2.2 Non - LID associated event counters ..................................................................................................................................................... 37
5.3.1 Non LID associated events .................................................................................................................................................................... 37
5.3.2 LID associated events ........................................................................................................................................................................... 37
5.3.2.1 Non critical events ...................................................................................................................................................................... 37
8.1.1 System reset ......................................................................................................................................................................................... 40
8.1.2 Power on sequence .............................................................................................................................................................................. 40
8.2.2 Logical Port activation and deactivation .................................................................................................................................................. 41
9.1.1 Direct register format ............................................................................................................................................................................. 45
9.1.2 Indirect register format ........................................................................................................................................................................... 45
9.2 Direct access registers ..................................................................................................................................................................................... 49
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APRIL 10, 2006
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
Table of Contents (Continued)
9.3 Indirect registers for SPI-3A module .................................................................................................................................................................. 54
9.3.1 Block base 0x0000 registers ................................................................................................................................................................. 55
9.3.2 Block base 0x0200 registers ................................................................................................................................................................. 55
9.3.3 Block base 0x0500 registers ................................................................................................................................................................. 56
9.3.4 Block base 0x0700 registers ................................................................................................................................................................. 57
9.3.5 Block base 0x0A00 registers ................................................................................................................................................................. 59
9.3.6 Block base 0x0C00 registers ................................................................................................................................................................. 59
9.3.7 Block base 0x0100 registers ................................................................................................................................................................. 62
9.3.8 Block base 0x1100 registers .................................................................................................................................................................. 62
9.3.9 Block base 0x1200 registers ................................................................................................................................................................. 62
9.3.10 Block base 0x1300 registers ............................................................................................................................................................... 63
9.3.11 Block base 0x1600 registers ................................................................................................................................................................ 64
9.3.12 Block base 0x1700 registers ............................................................................................................................................................... 64
9.3.13 Block base 0x1800 registers ............................................................................................................................................................... 64
9.3.14 Block base 0x1900 registers ............................................................................................................................................................... 65
9.4 Common module indirect registers (Module_base 0x8000) ............................................................................................................................... 66
9.4.1 Common module block base 0x0000 registers ....................................................................................................................................... 67
9.4.2 Common module block base 0x0100 registers ....................................................................................................................................... 67
9.4.3 Common module block base 0x0200 registers ....................................................................................................................................... 67
9.4.4 Common module block base 0x0300 registers ....................................................................................................................................... 67
9.4.5 Common module block base 0x0400 registers ....................................................................................................................................... 70
9.4.6 Common module block base 0x0500 registers ....................................................................................................................................... 70
9.4.7 Common module block base 0x0600 registers ....................................................................................................................................... 71
9.4.8 Common module block base 0x0700 registers ....................................................................................................................................... 71
9.4.9 Common module block base 0x0800 registers ....................................................................................................................................... 73
11.5 DC Electrical characteristics ............................................................................................................................................................................ 79
11.6 AC characteristics ........................................................................................................................................................................................... 80
11.6.3 SPI-4 LVTTL Status AC characteristics ................................................................................................................................................. 82
11.6.6.1 Microprocessor parallel port AC timing specifications .................................................................................................................. 83
11.6.6.2 Serial microprocessor interface (serial peripheral interface mode) .............................................................................................. 87
14. Datasheet Document Revision History .............................................................................................................................................................. 95
15. Ordering information ........................................................................................................................................................................................... 96
3
APRIL 10, 2006
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
List of Figures
Figure 1. Typical application: optical port and NPU/Traffic Manager .................................................................................................................................. 8
Figure 2. Data Path Diagram ........................................................................................................................................................................................... 8
Figure 3. Link mode SPI-3 ingress interface ................................................................................................................................................................... 14
Figure 7. Data sampling diagram ................................................................................................................................................................................... 18
Figure 8. SPI-4 ingress state diagram ............................................................................................................................................................................ 19
Figure 9. SPI-4 egress status state diagram ................................................................................................................................................................... 21
Figure 11. Definition of data flows ................................................................................................................................................................................... 23
Figure 12. Logical view of datapath configuration using PFPs ......................................................................................................................................... 24
Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor ............................................................................................................................. 25
Figure 14. SPI-3 ingress LP to LID map ........................................................................................................................................................................ 27
Figure 15. SPI-4 egress LID to LP map ......................................................................................................................................................................... 28
Figure 16. SPI-3 ingress to SPI-4 egress datapath ........................................................................................................................................................ 28
Figure 17. SPI-3 ingress to SPI-4 egress flow control path ............................................................................................................................................. 29
Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor ............................................................................................................................. 30
Figure 19. SPI-4 ingress to SPI-3 egress datapath ........................................................................................................................................................ 31
Figure 20. SPI-4 ingress to SPI-3 egress flow control ..................................................................................................................................................... 32
Figure 21 . Microprocessor data capture buffer .............................................................................................................................................................. 33
Figure 32. DDR interface and eye opening check through over sampling ....................................................................................................................... 43
Figure 33. Direct & indirect access ................................................................................................................................................................................. 45
Figure 42. IDT88P8341 820PBGA package, top and side views .................................................................................................................................... 93
Table 10 – Both attached devices start from reset status .................................................................................................................................................. 20
Table 11 – Ingress out of synch, egress in synch ........................................................................................................................................................... 20
Table 12 – Ingress in synch, egress out of synch ........................................................................................................................................................... 20
Table 13 - DIRECTION code assignment ...................................................................................................................................................................... 26
Table 15 - Zero margin SPI-3 timing budget ................................................................................................................................................................... 42
Table 16 - Margin check for SPI-3 timing ........................................................................................................................................................................ 42
Table 17 - Bit order within an 8-Bit data register ............................................................................................................................................................. 45
Table 18 - Bit order within a 32-Bit data register ............................................................................................................................................................. 45
Table 19 - Bit order within an 8-Bit data register ............................................................................................................................................................. 45
Table 20 - Bit order within a 16-Bit address register ....................................................................................................................................................... 46
Table 21 - Bit order within an 8-Bit control register .......................................................................................................................................................... 46
Table 22 - Module base address (Module_base) ........................................................................................................................................................... 46
Table 23 - Indirect access block bases for Module A ....................................................................................................................................................... 46
Table 24 - Indirect access block bases for common module ............................................................................................................................................ 47
Table 25 - Indirect access data registers (direct accessed space) at 0x30 to 0x33 .......................................................................................................... 47
Table 26 - Indirect access address register (direct accessed space) at 0x34 to 0x35 ...................................................................................................... 47
Table 27 - Indirect access control register (direct accessed space) at 0x3F ..................................................................................................................... 47
Table 29 - Direct mapped Module A registers ................................................................................................................................................................ 49
Table 30 - Direct mapped other registers ....................................................................................................................................................................... 49
Table 31 - SPI-3 data capture control register (register 0x00 ) ....................................................................................................................................... 49
Table 39 - Software reset register (0x20 in the direct accessed space) ........................................................................................................................... 51
Table 40 - SPI-4 status register (0x22 in the direct accessed space) ............................................................................................................................... 51
Table 41 - SPI-4 enable register (0x23 in the direct accessed space) ............................................................................................................................. 51
Table 42 - Module status register (0x24 in the direct accessed space) ............................................................................................................................ 52
Table 43 - Module enable register (0x28 in the direct accessed space) .......................................................................................................................... 52
Table 44 - Primary interrupt status register (0x2C in the direct accessed space) ............................................................................................................. 53
Table 45 - Secondary interrupt status register (0x2D in the direct accessed space) ........................................................................................................ 53
Table 46 - Primary interrupt enable register (0x2E in the direct accessed space) ............................................................................................................ 53
Table 47 - Secondary interrupt enable register (0x2F in the direct accessed space) ....................................................................................................... 53
Table 48 - Module A indirect register .............................................................................................................................................................................. 54
Table 49 - SPI-3 ingress LP to LID map ......................................................................................................................................................................... 55
Table 50 - SPI-3 general configuration register (register_offset=0x00) ............................................................................................................................ 55
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