Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> 88P8344BHGI

88P8344BHGI: 产品描述Microprocessor Circuit, CMOS, PBGA820, GREEN, PLASTIC, BGA-820; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小682KB，共98页; 制造商IDT (Integrated Device Technology); 标准

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88P8344BHGI概述

Microprocessor Circuit, CMOS, PBGA820, GREEN, PLASTIC, BGA-820

88P8344BHGI规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
零件包装代码	BGA
包装说明	GREEN, PLASTIC, BGA-820
针数	820
Reach Compliance Code	compliant
ECCN代码	EAR99
Is Samacsys	N
JESD-30 代码	S-PBGA-B820
JESD-609代码	e3
长度	35 mm
端子数量	820
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA820,34X34,40
封装形状	SQUARE
封装形式	GRID ARRAY
峰值回流温度（摄氏度）	260
电源	1.8,3.3 V
认证状态	Not Qualified
座面最大高度	2.44 mm
最大供电电压	1.96 V
最小供电电压	1.68 V
标称供电电压	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	MATTE TIN
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	35 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR CIRCUIT
Base Number Matches	1

文档解析

这份文档是关于IDT88P8344 SPI Exchange的数据手册，提供了详细的技术信息，包括但不限于以下方面：

产品规格：文档提供了IDT88P8344芯片的全面规格，包括其工业温度范围的适用性。
功能描述：详细介绍了IDT88P8344的主要功能，如低速到高速的SPI交换设备、逻辑端口映射、可配置的内存分配、掩蔽中断、数据流控制等。
接口标准：描述了IDT88P8344支持的标准接口，包括四个OIF SPI-3接口和一个OIF SPI-4接口，以及它们的参数和特性。
性能监控：提供了一整套性能监控计数器，用于跟踪数据包数量、数据片段、错误和字节等。
应用场景：列举了IDT88P8344的应用领域，如以太网传输、SONET/SDH数据包传输线卡、宽带聚合、多服务交换机和IP服务设备。
数据路径和流控制：详细描述了数据在IDT88P8344内部的传输路径，以及如何通过逻辑标识符（LID）映射在SPI-3和SPI-4接口之间进行数据交换。
配置和操作：提供了硬件操作和软件操作的指南，包括系统重置、上电序列、时钟域、芯片配置序列、逻辑端口激活和停用、缓冲段修改等。
寄存器描述：详细列出了IDT88P8344的直接访问寄存器和间接访问寄存器，以及它们的功能和用途。
电气和热特性：提供了芯片的绝对最大额定值、推荐操作条件、端接电容、热特性和直流电气特性。
物理特性：描述了芯片的封装、引脚布局和设备概览。
JTAG接口：介绍了JTAG接口的功能和使用。
时钟发生器：解释了时钟发生器如何从SPI-4入口时钟或REF_CLK输入针生成时钟，并提供了时钟输出的配置信息。
回环测试：描述了SPI-3物理端口的本地回环支持。
性能监控和诊断：提供了性能监控和诊断模块的详细信息，包括事件计数器和中断指示。
布局指南：提供了印刷电路板布局的推荐指南，以确保信号完整性和减少噪声。
版本和修订历史：记录了数据手册的修订历史，包括对内容的更新和更改。
订购信息：提供了如何订购IDT88P8344产品的指导。

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SPI EXCHANGE 4 x SPI-3 TO SPI-4

Issue 1.0

FEATURES

•

IDT88P8344

Functionality

Low speed to high speed SPI exchange device

Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction

Per LP configurable memory allocation

Maskable interrupts for fatal errors

Fragment and burst length configurable per interface: min 16 bytes,

max 256 bytes

•

Standard Interfaces

Four OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64

concurrently active LPs per interface

- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256

concurrently active LPs

- SPI-4 FIFO status channel options:

•

LVDS full-rate

•

LVTTL eighth-rate

- Compatible with Network Processor Streaming Interface (NPSI)

NPE-Framer mode of operation

- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the

entire frequency range

- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle

- IEEE 1149.1 JTAG

- Serial or parallel microprocessor interface for control and monitoring

•

Full Suite of Performance Monitoring Counters

Number of packets

APPLICATIONS

•

Number of fragments

Number of errors

Number of bytes

Green parts available, see ordering information

Ethernet transport

SONET / SDH packet transport line cards

Broadband aggregation

Multi-service switches

IP services equipment

DESCRIPTION

The IDT88P8344 is a SPI (System Packet Interface) Exchange with four SPI-

3 interfaces and one SPI-4 interface. The data that enter on the low speed

interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for

transmission over the high speed interface (SPI-4). The data that enter on the

high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and

enqueued for transmission over a low speed interface (SPI-3). A data flow

between SPI-3 and SPI-4 interfaces is accomplished with LID maps. The logical

port addresses and number of entries in the LID maps may be dynamically

configured. Various parameters of a data flow may be configured by the user

such as buffer memory size and watermarks. In a typical application, the

IDT88P8344 enables connection of multiple SPI-3 devices to a SPI-4 network

processor. In other applications SPI-3 or SPI-4 devices may be connected to

multiple SPI-3 network processors or traffic managers.

HIGH LEVEL FUNCTIONAL BLOCK DIAGRAM

SPI-3 A

64 Logical Ports

SPI-3 to SPI-4 PFP

SPI-4 to SPI-3 PFP

SPI-3 B

64 Logical Ports

SPI-3 to SPI-4 PFP

SPI-4 to SPI-3 PFP

SPI-3 C

64 Logical Ports

SPI-3 to SPI-4 PFP

SPI-4 to SPI-3 PFP

SPI-4

256

Logical

Ports

SPI-3 D

64 Logical Ports

SPI-3 to SPI-4 PFP

SPI-4 to SPI-3 PFP

JTAG IF

Uproc IF

Clock Generator

Control Path

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

Data Path

PFP = Packet Fragment Processor

6370 drw01

INDUSTRIAL TEMPERATURE RANGE

2006

APRIL 2006

DSC-6370/7

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

Table of Contents

Features ........................................................................................................................................................................................................................ 1

Applications .................................................................................................................................................................................................................. 1

1. Introduction ............................................................................................................................................................................................................. 8

2. Pin description ......................................................................................................................................................................................................... 9

3. External interfaces ................................................................................................................................................................................................. 13

3.1 SPI-3 ............................................................................................................................................................................................................... 13

3.1.1 SPI-3 ingress ........................................................................................................................................................................................ 13

3.1.2 SPI-3 egress ........................................................................................................................................................................................ 15

3.2 SPI-4 ............................................................................................................................................................................................................... 17

3.2.1 SPI-4 ingress ........................................................................................................................................................................................ 17

3.2.2 SPI-4 egress ........................................................................................................................................................................................ 20

3.2.3 SPI-4 startup handshake ....................................................................................................................................................................... 20

3.3 Microprocessor interface .................................................................................................................................................................................. 22

4. Datapath and flow control .................................................................................................................................................................................... 23

4.1 SPI-3 to SPI-4 datapath and flow control .......................................................................................................................................................... 25

4.2 SPI-4 to SPI-3 datapath and flow control .......................................................................................................................................................... 30

4.3 SPI-3 ingress to SPI-3 egress datapath ............................................................................................................................................................ 33

4.4 Microprocessor interface to SPI-3 datapath ...................................................................................................................................................... 34

4.4.1 SPI-3 to ingress microprocessor interface datapath ................................................................................................................................ 34

4.4.2 Microprocessor insert to SPI-3 egress datapath ..................................................................................................................................... 35

4.4.3 Microprocessor interface to SPI-4 egress datapath ................................................................................................................................ 36

4.4.4 SPI-4 ingress to microprocessor interface datapath ................................................................................................................................ 37

5. Performance monitor and diagnostics ................................................................................................................................................................. 38

5.1 Mode of operation ............................................................................................................................................................................................ 38

5.2 Counters ......................................................................................................................................................................................................... 38

5.2.1 LID associated event counters ............................................................................................................................................................... 38

5.2.2 Non - LID associated event counters ..................................................................................................................................................... 38

5.3 Captured events .............................................................................................................................................................................................. 38

5.3.1 Non LID associated events .................................................................................................................................................................... 38

5.3.2 LID associated events ........................................................................................................................................................................... 38

5.3.2.1 Non critical events ...................................................................................................................................................................... 38

5.3.2.2 Critical events ............................................................................................................................................................................. 38

5.3.3 Timebase .............................................................................................................................................................................................. 38

5.3.3.1 Internally generated timebase ..................................................................................................................................................... 38

5.3.3.2 Externally generated timebase .................................................................................................................................................... 38

6. Clock generator ...................................................................................................................................................................................................... 39

7. Loopbacks .............................................................................................................................................................................................................. 40

7.1 SPI-3 Loopback ............................................................................................................................................................................................... 40

8. Operation guide ..................................................................................................................................................................................................... 41

8.1 Hardware operation ........................................................................................................................................................................................ 41

8.1.1 System reset ......................................................................................................................................................................................... 41

8.1.2 Power on sequence .............................................................................................................................................................................. 41

8.1.3 Clock domains ...................................................................................................................................................................................... 41

8.2 Software operation ........................................................................................................................................................................................... 41

8.2.1 Chip configuration sequence ................................................................................................................................................................. 41

8.2.2 Logical Port activation and deactivation .................................................................................................................................................. 42

8.2.3 Buffer segment modification .................................................................................................................................................................... 42

8.2.4 Manual SPI-4 ingress LVDS bit alignment .............................................................................................................................................. 42

8.2.5 SPI-4 status channel software ............................................................................................................................................................... 43

8.2.6 IDT88P8344 layout guidelines .............................................................................................................................................................. 43

8.2.7 Software Eye-Opening Check on SPI-4 Interface .................................................................................................................................. 44

9. Register description .............................................................................................................................................................................................. 46

9.1 Register access summary ................................................................................................................................................................................ 46

9.1.1 Direct register format ............................................................................................................................................................................. 46

9.1.2 Indirect register format ........................................................................................................................................................................... 46

9.2 Direct access registers ..................................................................................................................................................................................... 50

APRIL 10, 2006

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

Table of Contents (Continued)

9.3 Indirect registers for SPI-3A, SPI-3B, SPI-3C, SPI-3D modules ........................................................................................................................ 56

9.3.1 Block base 0x0000 registers ................................................................................................................................................................. 57

9.3.2 Block base 0x0200 registers ................................................................................................................................................................. 57

9.3.3 Block base 0x0500 registers ................................................................................................................................................................. 58

9.3.4 Block base 0x0700 registers ................................................................................................................................................................. 59

9.3.5 Block base 0x0A00 registers ................................................................................................................................................................. 61

9.3.6 Block base 0x0C00 registers ................................................................................................................................................................. 61

9.3.7 Block base 0x1000 registers ................................................................................................................................................................. 64

9.3.8 Block base 0x1100 registers .................................................................................................................................................................. 64

9.3.9 Block base 0x1200 registers ................................................................................................................................................................. 64

9.3.10 Block base 0x1300 registers ............................................................................................................................................................... 65

9.3.11 Block base 0x1600 registers ................................................................................................................................................................ 66

9.3.12 Block base 0x1700 registers ............................................................................................................................................................... 66

9.3.13 Block base 0x1800 registers ............................................................................................................................................................... 66

9.3.14 Block base 0x1900 registers ............................................................................................................................................................... 67

9.4 Common module indirect registers (Module_base 0x8000) ............................................................................................................................... 68

9.4.1 Common module block base 0x0000 registers ....................................................................................................................................... 69

9.4.2 Common module block base 0x0100 registers ....................................................................................................................................... 69

9.4.3 Common module block base 0x0200 registers ....................................................................................................................................... 69

9.4.4 Common module block base 0x0300 registers ....................................................................................................................................... 69

9.4.5 Common module block base 0x0400 registers ....................................................................................................................................... 72

9.4.6 Common module block base 0x0500 registers ....................................................................................................................................... 72

9.4.7 Common module block base 0x0600 registers ....................................................................................................................................... 73

9.4.8 Common module block base 0x0700 registers ....................................................................................................................................... 73

9.4.9 Common module block base 0x0800 registers ....................................................................................................................................... 75

10. JTAG interface ....................................................................................................................................................................................................... 79

11. Electrical and Thermal Specifications ................................................................................................................................................................ 79

11.1 Absolute maximum ratings ............................................................................................................................................................................... 79

11.2 Recommended Operating Conditions .............................................................................................................................................................. 79

11.3 Terminal Capacitance ..................................................................................................................................................................................... 80

11.4 Thermal Characteristics .................................................................................................................................................................................. 80

11.5 DC Electrical characteristics ............................................................................................................................................................................ 81

11.6 AC characteristics ........................................................................................................................................................................................... 82

11.6.1 SPI-3 I/O timing ................................................................................................................................................................................... 82

11.6.2 SPI-4 LVDS Input / Output ................................................................................................................................................................... 83

11.6.3 SPI-4 LVTTL Status AC characteristics ................................................................................................................................................. 84

11.6.4 REF_CLK clock input .......................................................................................................................................................................... 84

11.6.5 MCLK internal clock and OCLK[3:0] clock outputs ................................................................................................................................ 84

11.6.6 Microprocessor interface ..................................................................................................................................................................... 84

11.6.6.1 Microprocessor parallel port AC timing specifications .................................................................................................................. 85

11.6.6.2 Serial microprocessor interface (serial peripheral interface mode) .............................................................................................. 89

12. Mechanical characteristics .................................................................................................................................................................................. 90

12.1 Device overview ........................................................................................................................................................................................... 90

12.2 Pin name/ball location table ............................................................................................................................................................................ 91

12.3 Device package ............................................................................................................................................................................................. 94

13. Glossary ................................................................................................................................................................................................................ 96

14. Datasheet Document Revision History .............................................................................................................................................................. 97

15. Ordering information ........................................................................................................................................................................................... 98

APRIL 10, 2006

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

List of Figures

Figure 1. Typical application: NPU, PHY, and co-processor ............................................................................................................................................. 8

Figure 2. Data path diagram ............................................................................................................................................................................................ 8

Figure 3. Link mode SPI-3 ingress interface ................................................................................................................................................................... 14

Figure 4. PHY mode SPI-3 ingress interface .................................................................................................................................................................. 14

Figure 5. Link mode SPI-3 egress interface .................................................................................................................................................................... 16

Figure 6. PHY mode SPI-3 egress interface ................................................................................................................................................................... 16

Figure 7. Data sampling diagram ................................................................................................................................................................................... 18

Figure 8. SPI-4 ingress state diagram ............................................................................................................................................................................ 19

Figure 9. SPI-4 egress status state diagram ................................................................................................................................................................... 21

Figure 10. Interrupt scheme ........................................................................................................................................................................................... 22

Figure 11. Definition of data flows ................................................................................................................................................................................... 23

Figure 12. Logical view of datapath configuration using PFPs ......................................................................................................................................... 24

Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor ............................................................................................................................. 25

Figure 14. SPI-3 ingress LP to LID map ........................................................................................................................................................................ 27

Figure 15. SPI-4 egress LID to LP map ......................................................................................................................................................................... 28

Figure 16. SPI-3 ingress to SPI-4 egress datapath ........................................................................................................................................................ 28

Figure 17. SPI-3 ingress to SPI-4 egress flow control path ............................................................................................................................................. 29

Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor ............................................................................................................................. 30

Figure 19. SPI-4 ingress to SPI-3 egress datapath ........................................................................................................................................................ 31

Figure 20. SPI-4 ingress to SPI-3 egress flow control ..................................................................................................................................................... 32

Figure 21. SPI-3 ingress to SPI-3 egress datapath ........................................................................................................................................................ 33

Figure 22 . Microprocessor data capture buffer .............................................................................................................................................................. 34

Figure 23. SPI-3 ingress to microprocessor capture interface datapath ........................................................................................................................... 34

Figure 25. Microprocessor interface to SPI-3 egress detailed datapath diagram .............................................................................................................. 35

Figure 24 . Microprocessor data insert buffer ................................................................................................................................................................. 35

Figure 26. Microprocessor data insert buffer .................................................................................................................................................................. 36

Figure 27. Microprocessor data insert interface to SPI-4 egress datapath ....................................................................................................................... 36

Figure 28. Microprocessor data capture buffer ............................................................................................................................................................... 37

Figure 29. SPI-4 ingress to microprocessor data capture interface path .......................................................................................................................... 37

Figure 30. Clock generator ............................................................................................................................................................................................ 39

Figure 31. SPI-3 Loopback diagram .............................................................................................................................................................................. 40

Figure 32. Power-on-Reset Sequence .......................................................................................................................................................................... 41

Figure 33. DDR interface and eye opening check through over sampling ....................................................................................................................... 44

Figure 34. Direct & indirect access ................................................................................................................................................................................. 46

Figure 35. SPI-3 I/O timing diagram ............................................................................................................................................................................... 82

Figure 36. SPI-4 I/O timing diagram ............................................................................................................................................................................... 83

Figure 37. Microprocessor parallel port Motorola read timing diagram ............................................................................................................................ 85

Figure 38. Microprocessor parallel port Motorola write timing diagram ............................................................................................................................ 86

Figure 39. Microprocessor parallel port Intel mode read timing diagram .......................................................................................................................... 87

Figure 40. Microprocessor parallel port Intel mode write timing diagram .......................................................................................................................... 88

Figure 41. Microprocessor serial peripheral interface timing diagram .............................................................................................................................. 89

Figure 42. IDT88P8344 820PBGA package, bottom view .............................................................................................................................................. 94

Figure 43. IDT88P8344 820PBGA package, top and side views .................................................................................................................................... 95

APRIL 10, 2006

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

List of Tables

Table 1 – I/O types .......................................................................................................................................................................................................... 9

Table 2 – SPI-3 ingress interface pin definition .................................................................................................................................................................. 9

Table 3 – SPI-3 egress interface pin definition ................................................................................................................................................................ 10

Table 4 – SPI-3 status interface pin definition .................................................................................................................................................................. 10

Table 5 – SPI-4 ingress interface definition ..................................................................................................................................................................... 11

Table 6 – SPI-4 egress interface definition ...................................................................................................................................................................... 11

Table 7 – Parallel microprocessor interface .................................................................................................................................................................... 12

Table 8 – Serial microprocessor interface (serial peripheral interface mode) ................................................................................................................... 12

Table 9 – Miscellaneous ................................................................................................................................................................................................ 12

Table 10 – Both attached devices start from reset status .................................................................................................................................................. 20

Table 11 – Ingress out of synch, egress in synch ........................................................................................................................................................... 20

Table 12 – Ingress in synch, egress out of synch ........................................................................................................................................................... 20

Table 13 - DIRECTION code assignment ...................................................................................................................................................................... 26

Table 14 – CK_SEL[3:0] input pin encoding ................................................................................................................................................................... 39

Table 15 - Zero margin SPI-3 timing budget ................................................................................................................................................................... 43

Table 16 - Margin check for SPI-3 timing ........................................................................................................................................................................ 43

Table 17 - Bit order within an 8-Bit data register ............................................................................................................................................................. 46

Table 18 - Bit order within a 32-Bit data register ............................................................................................................................................................. 46

Table 19 - Bit order within an 8-Bit data register ............................................................................................................................................................. 46

Table 20 - Bit order within a 16-Bit address register ....................................................................................................................................................... 47

Table 21 - Bit order within an 8-Bit control register .......................................................................................................................................................... 47

Table 22 - Module base address (Module_base) ........................................................................................................................................................... 47

Table 23 - Indirect access block bases for Module A, Module B, Module C, and Module D ............................................................................................. 47

Table 24 - Indirect access block bases for common module ............................................................................................................................................ 48

Table 25 - Indirect access data registers (direct accessed space) at 0x30 to 0x33 .......................................................................................................... 48

Table 26 - Indirect access address register (direct accessed space) at 0x34 to 0x35 ...................................................................................................... 48

Table 27 - Indirect access control register (direct accessed space) at 0x3F ..................................................................................................................... 48

Table 28 - Error coding table ......................................................................................................................................................................................... 49

Table 29 - Direct mapped Module A, Module B, Module C, and Module D registers ........................................................................................................ 50

Table 30 - Direct mapped other registers ....................................................................................................................................................................... 50

Table 31 - SPI-3 data capture control register (registers 0x00, 0x08, 0x10, 0x18) ......................................................................................................... 50

Table 32 - SPI-3 data Capture register (registers 0x01, 0x09, 0x11, 0x19) .................................................................................................................... 50

Table 33 - SPI-4 data insert control register (registers 0x02, 0x0A, 0x12, 0x1A) ............................................................................................................ 51

Table 34 - SPI-4 data insert register (registers 0x03, 0x0B, 0x13, 0x1B) ....................................................................................................................... 51

Table 35 - SPI-4 data capture control register (registers 0x04, 0x0C, 0x14, 0x1C) ........................................................................................................ 51

Table 36 - SPI-3 data insert control register (registers 0x05, 0x0D, 0x15, 0x1D) ........................................................................................................... 51

Table 37 - SPI-4 data capture register (registers 0x06, 0x0E, 0x16, 0x1E) .................................................................................................................... 51

Table 38 - SPI-3 data insert register (registers 0x07, 0x0F, 0x17, 0x1F) ....................................................................................................................... 51

Table 39 - Software reset register (0x20 in the direct accessed space) ........................................................................................................................... 52

Table 40 - SPI-4 status register (0x22 in the direct accessed space) ............................................................................................................................... 52

Table 41 - SPI-4 enable register (0x23 in the direct accessed space) ............................................................................................................................. 52

Table 42 - Module status register (0x24 to 0x27 in the direct accessed space) ................................................................................................................ 53

Table 43 - Module enable register (0x28 to 0x2B in the direct accessed space) ............................................................................................................. 53

Table 44 - Primary interrupt status register (0x2C in the direct accessed space) ............................................................................................................. 54

Table 45 - Secondary interrupt status register (0x2D in the direct accessed space) ........................................................................................................ 54

Table 46 - Primary interrupt enable register (0x2E in the direct accessed space) ............................................................................................................ 55

Table 47 - Secondary interrupt enable register (0x2F in the direct accessed space) ....................................................................................................... 55

Table 48 - Module A/B/C/D indirect register .................................................................................................................................................................... 56

Table 49 - SPI-3 ingress LP to LID map ......................................................................................................................................................................... 57

Table 50 - SPI-3 general configuration register (register_offset=0x00) ............................................................................................................................ 57

Table 51 - SPI-3 ingress configuration register (register_offset=0x01) ............................................................................................................................. 58

Table 52 - SPI-3 ingress fill level register (register_offset=0x02) ..................................................................................................................................... 58

Table 53 - SPI-3 ingress max fill level register (register_offset=0x03) .............................................................................................................................. 58

Table 54 - SPI-3 egress LID to LP map ......................................................................................................................................................................... 58

Table 55 - SPI-3 egress configuration register (register_offset=0x00) ............................................................................................................................. 59

Table 56 - SPI-4 ingress to SPI-3 egress flow control register (register_offset=0x01) ...................................................................................................... 59

APRIL 10, 2006

88P8344BHGI

88P8344BHGI在线购买

88P8344BHGI概述

88P8344BHGI规格参数

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