The SN54F299 is obsolete and no
longer supplied.
SN54F299, SN74F299
8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3 STATE OUTPUTS
SDFS071B − MARCH 1987 − REVISED APRIL 2004
D
Four Modes of Operation:
− Hold (Store)
− Shift Right
− Shift Left
− Load Data
Operates With Outputs Enabled or at High
Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Direct Overriding Clear
Applications:
− Stacked or Pushdown Registers
− Buffer Storage
− Accumulator Registers
SN54F299 . . . J PACKAGE
SN74F299 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
D
D
D
D
D
S0
OE1
OE2
G/Q
G
E/Q
E
C/Q
C
A/Q
A
Q
A′
CLR
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
S1
SL
Q
H′
H/Q
H
F/Q
F
D/Q
D
B/Q
B
CLK
SR
description/ordering information
These 8-bit universal shift /storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two
output-enable (OE1, OE2) inputs can be used to
choose the modes of operation listed in the
function table.
SN54F299 . . . FK PACKAGE
(TOP VIEW)
Synchronous parallel loading is accomplished by
taking both S0 and S1 high. This places the
3-state outputs in a high-impedance state and
permits data that is applied on the I/O ports to
be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in
any mode. Clearing occurs when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs
but has no effect on clearing, shifting, or storage of data.
ORDERING INFORMATION
TA
PDIP − N
0°C to 70°C
SOIC − DW
SOP − NS
PACKAGE†
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
ORDERABLE
PART NUMBER
SN74F299N
SN74F299DW
SN74F299DWR
SN74F299NSR
F299
74F299
TOP-SIDE
MARKING
SN74F299N
G/Q
G
E/Q
E
C/Q
C
A/Q
A
Q
A′
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
OE2
OE1
S0
VCC
S1
SL
Q
H′
H/Q
H
F/Q
F
D/Q
D
Copyright
2004, Texas Instruments Incorporated
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
CLR
GND
SR
CLK
B/Q
B
1
SDFS071B − MARCH 1987 − REVISED APRIL 2004
SN54F299, SN74F299
8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3 STATE OUTPUTS
FUNCTION TABLE
INPUTS
MODE
CLR
L
L
L
H
H
H
H
H
H
H
S1
X
L
H
L
X
L
L
H
H
H
S0
L
X
H
L
X
H
H
L
L
H
OE1†
L
L
X
L
L
L
L
L
L
X
OE2†
L
L
X
L
L
L
L
L
L
X
CLK
X
X
X
X
L
↑
↑
↑
↑
↑
SL
X
X
X
X
X
X
X
H
L
X
SR
X
X
X
X
X
H
L
X
X
X
A/QA
L
L
X
QA0
QA0
H
L
QBn
QBn
a
B/QB
L
L
X
QB0
QB0
QAn
QAn
QCn
QCn
b
C/QC
L
L
X
QC0
QC0
QBn
QBn
QDn
QDn
c
The SN54F299 is obsolete and no
longer supplied.
I/O PORTS
D/QD
L
L
X
QD0
QD0
QCn
QCn
QEn
QEn
d
E/QE
L
L
X
QE0
QE0
QDn
QDn
QFn
QFn
e
F/QF
L
L
X
QF0
QF0
QEn
QEn
QGn
QGn
f
G/QG
L
L
X
QG0
QG0
QFn
QFn
QHn
QHn
g
H/QH
L
L
X
QH0
QH0
QGn
QGn
H
L
h
OUTPUTS
QA′
L
L
L
QA0
QA0
H
L
QBn
QBn
a
QH′
L
L
L
QH0
QH0
QGn
QGn
H
L
h
Clear
Hold
Shift
Right
Shift
Left
Load
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop
outputs are isolated from the I/O terminals.
† When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
logic diagram (positive logic)
S0
1
S1
SR
(shift right
serial input)
19
18
11
Six
Identical
Channels
Not
Shown‡
12
1D
C1
R
R
17
QH′
8
9
2
3
7
A /QA
16
H /QH
1D
C1
SL
(shift left
serial input)
CLK
QA′
CLR
OE1
OE2
‡ I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
The SN54F299 is obsolete and no
longer supplied.
SN54F299, SN74F299
8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3 STATE OUTPUTS
SDFS071B − MARCH 1987 − REVISED APRIL 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
Current into any output in the low state: Q
A′
or Q
H′
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
SN54F299 (Q
A
thru Q
H
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
SN74F299 (Q
A
thru Q
H
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Package thermal impedance,
θ
JA
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54F299
MIN
VCC
VIH
VIL
IIK
IOH
IOL
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
QA′ or QH′
QA thru QH
QA′ or QH′
QA thru QH
4.5
2
0.8
−18
−1
−3
20
20
NOM
5
MAX
5.5
SN74F299
MIN
4.5
2
0.8
−18
−1
−3
20
24
mA
mA
NOM
5
MAX
5.5
UNIT
V
V
V
mA
TA
Operating free-air temperature
−55
125
0
70
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SDFS071B − MARCH 1987 − REVISED APRIL 2004
SN54F299, SN74F299
8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3 STATE OUTPUTS
The SN54F299 is obsolete and no
longer supplied.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
QA′ or QH′
VOH
QA thru QH
Any output
QA′ or QH′
VOL
QA thru QH
A thru H
II
IIH‡
Any other
A thru H
Any other
A thru H
IIL‡
S0 or S1
Any other
VCC = 5.5 V,
VI = 0.5 V
VCC = 5.5 V,
VI = 2.7 V
VCC = 5.5 V
VCC = 4.5 V
VCC = 4.5 V
VCC = 4.75 V,
VCC = 4.5 V,
TEST CONDITIONS
II = − 18 mA
IOH = − 1 mA
IOH = − 1 mA
IOH = − 3 mA
IOH = − 1 mA to − 3 mA
IOL = 20 mA
IOL = 20 mA
IOL = 24 mA
VI = 5.5 V
VI = 7 V
SN54F299
MIN TYP†
MAX
−1.2
2.5
2.5
2.4
3.4
3.4
3.3
0.3
0.3
0.5
0.5
0.35
1
0.1
70
20
−0.65
−1.2
−0.6
0.5
1
0.1
70
20
−0.65
−1.2
−0.6
−150
95
mA
mA
mA
mA
µA
A
2.5
2.5
2.4
2.7
0.3
0.5
V
3.4
3.4
3.3
V
SN74F299
MIN TYP†
MAX
−1.2
UNIT
V
IOS§
VCC = 5.5 V,
VO = 0
−60
−150
−60
ICC
VCC = 5.5 V,
See Note 4
68
95
68
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 4: ICC is measured with OE1, OE2, and CLK at 4.5 V.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
′F299
MIN
fclock
tw
Clock frequency
CLK high or low
Pulse duration
Setup time before
CLK↑
Inactive-state setup
time before CLK↑¶
Hold time after CLK↑
CLR low
S0 or S1
A/QA thru H/QH, SR, or SL
CLR
S0 or S1
th
A /QA thru H /QH, SR, or SL
¶ Inactive-state setup time also is referred to as recovery time.
High or low
High or low
High
High or low
High or low
7
7
8.5
5.5
7
0
2
MAX
70
8
8
9.5
6.5
13
0
2
MIN
MAX
65
7
7
8.5
5.5
7
0
2
ns
ns
ns
MIN
MAX
70
MHz
SN54F299
SN74F299
UNIT
tsu
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
The SN54F299 is obsolete and no
longer supplied.
SN54F299, SN74F299
8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3 STATE OUTPUTS
SDFS071B − MARCH 1987 − REVISED APRIL 2004
switching characteristics (see Figure 1)
VCC = 5 V,
CL = 50 pF,
RL = 500
Ω,
TA = 25°C
′F299
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
70
3.2
CLK
CLK
QA or QH
A′
H′
QA thru QH
QA′ or QH′
QA thru QH
QA thru QH
QA thru QH
2.7
3.2
4.2
3.7
5.7
2.7
OE1 or OE2
OE1 or OE2
3.2
1.7
1.2
TYP
100
6.6
6.1
6.6
8.1
7.1
10.6
5.6
6.6
4.1
3.6
9
8.5
9
11
9.5
14
8
10
6
5.5
MAX
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
Ω,
TA = MIN to MAX†
SN54F299
MIN
65
2.7
2.2
2.7
3.7
3.2
5
2.2
2.7
1.7
1.2
10.5
10
11
12.5
11.5
15.5
10.5
12
9
7.5
MAX
SN74F299
MIN
70
3.2
2.7
3.2
4.2
3.7
5.7
2.7
3.2
1.7
1.2
10
9.5
10
12
10.5
15
9
11
7
6.5
ns
ns
ns
ns
ns
MAX
MHz
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
CLR
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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