‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded if the input current ratings are observed.
2
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SDFS095B − NOVEMBER 1993 − REVISED JANUARY 1996
SN74F2244
25
Ω
OCTAL BUFFER/DRIVER
WITH 3 STATE OUTPUTS
recommended operating conditions
MIN
VCC
VIH
VIL
IIK
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature
0
4.5
2
0.8
−18
− 15
12
70
NOM
5
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V
VCC = 4.75 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
Any OE input
IIL
IOS‡
ICC
Any A input
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
Outputs open
VI = 0.5 V
VO = 0
Outputs high
Outputs low
Outputs disabled
−100
40
60
60
TEST CONDITIONS†
II = − 18 mA
IOH = − 3 mA
IOH = − 15 mA
IOH = − 3 mA
IOL = 1 mA
IOL = 12 mA
VI = 0.5 V
VO = 7 V
VO = 2.7 V
VI = 2.7 V
MIN
2.4
2
2.7
0.2
0.5
0.5
0.75
0.1
50
−50
20
−1
− 1.6
−225
60
90
90
mA
mA
mA
V
mA
µA
µA
µA
TYP†
2.8
2.3
V
MAX
−1.2
UNIT
V
VOL
II
IOZH
IOZL
IIH
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics (see Figure 1)
VCC = 5 V,
CL = 50 PF,
R1 = 500
Ω,
R2 = 500
Ω,
TA = 25°C
MIN
MAX
1.5
2.5
1.5
2.5
1.5
1.5
7
8
9
11.5
9
8.5
VCC = 4.5 V TO 5.5 V,
CL = 50 PF,
R1 = 500
Ω,
R2 = 500
Ω,
TA = MIN TO MAX§
MIN
MAX
1.5
2
1
2.5
1
1.5
7
8
9.5
12
9.5
9.5
ns
ns
ns
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
A
OE
OE
Y
Y
Y
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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•
•
3
SDFS095B − NOVEMBER 1993 − REVISED JANUARY 1996
SN74F2244
25
Ω
OCTAL BUFFER/DRIVER
WITH 3 STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
Open
(all others)
From Output
Under Test
CL
(see Note A)
Test
Point
R2
RL = R1 = R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
R1
Test
Point
S1
R1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note C)
3V
1.5 V
tw
3V
1.5 V
0V
Timing Input
(see Note C)
tsu
Data Input
(see Note C)
1.5 V
3V
1.5 V
0V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Low-Level
Pulse
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Output
Control
(low-level enable)
Input
(see Note C)
tPLH
In-Phase
Output
(see Note E)
tPHL
Out-of-Phase
Output
(see Note E)
1.5 V
3V
1.5 V
1.5 V
0V
tPHL
1.5 V
1.5 V
VOL
tPLH
VOH
1.5 V
VOL
Waveform 2
(see Notes B and E)
tPZH
VOH
1.5 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
tPHZ
VOL
0.3 V
tPZL
tPLZ
3.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, tr = tf
≤
2.5 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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•
•
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74F2244DBLE
SN74F2244DBR
SN74F2244DW
SN74F2244DWR
SN74F2244N
(1)
Status
(1)
Package Type Package Pins Package
Drawing
Qty
SSOP
SSOP
SOIC
SOIC
PDIP
DB
DB
DW
DW
N
20
20
20
20
20
Eco Plan
(2)
Lead/Ball Finish
Call TI
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MSL Peak Temp
(3)
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Top-Side Markings
(4)
Samples
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
TBD
TBD
TBD
TBD
TBD
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The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The
information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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