CD54/74HC374, CD54/74HCT374,
CD54/74HC574, CD54/74HCT574
Data sheet acquired from Harris Semiconductor
SCHS183C
February 1998 - Revised May 2004
High-Speed CMOS Logic Octal D-Type Flip-Flop,
3-State Positive-Edge Triggered
Description
The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type
flip-flops with 3-state outputs and the capability to drive 15
LSTTL loads. The eight edge-triggered flip-flops enter data into
their registers on the LOW to HIGH transition of clock (CP). The
output enable (OE) controls the 3-state outputs and is
independent of the register operation. When OE is HIGH, the
outputs are in the high-impedance state. The 374 and 574 are
identical in function and differ only in their pinout arrangements.
Features
• Buffered Inputs
[ /Title
(CD74
HC374
,
CD74
HCT37
4,
CD74
HC574
,
CD74
HCT57
• Common Three-State Output Enable Control
• Three-State Outputs
• Bus Line Driving Capability
• Typical Propagation Delay (Clock to Q) = 15ns at
V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2-V to 6-V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC374F3A
CD54HC574F3A
CD54HCT374F3A
CD54HCT574F3A
CD74HC374E
CD74HC374M
CD74HC374M96
CD74HC574E
CD74HC574M
CD74HC574M96
CD74HCT374E
CD74HCT374M
CD74HCT374M96
CD74HCT574E
CD74HCT574M
CD74HCT574M96
CD74HCT574PWR
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2004, Texas Instruments Incorporated
1
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Pinouts
CD54HC374, CD54HCT374
(CERDIP)
CD74HC374, CD74HCT374
(PDIP, SOIC)
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
CD54HC574, CD54HCT574
(CERDIP)
CD74HC574
(PDIP, SOIC)
CD74HCT574
(PDIP, SOIC, TSSOP)
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
GND 10
GND 10
Functional Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
CP Q
CP
D
CP Q
D
CP
Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
OE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
TRUTH TABLE
INPUTS
OE
L
L
L
H
CP
↑
↑
L
X
Dn
H
L
X
X
OUTPUT
Qn
H
L
Q0
Z
H = High Level (Steady State)
L = Low Level (Steady State)
X= Don’t Care
↑=
Transition from Low to High Level
Q0= The level of Q before the indicated steady-state input
conditions were established
Z = High Impedance State
2
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V.
. . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1).
. . . . . . . . . . . . . . . . θ
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
I
V
CC
or
GND
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-
-6
-7.8
0.02
0.02
0.02
-
6
7.8
-
2
4.5
6
-
4.5
6
2
4.5
6
-
4.5
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
3
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
SYMBOL
I
CC
V
I
(V)
V
CC
or
GND
I
O
(mA)
0
-
25
o
C
MIN
-
-
TYP
-
-
MAX
8
±0.5
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
-
-
MAX
80
±5.0
MIN
-
-
MAX
160
±10
UNITS
µA
µA
V
CC
(V)
6
6
Three- State Leakage V
IL
or V
IH
V
O
= V
CC
or GND
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
I
I
I
CC
V
CC
and
GND
V
CC
or
GND
V
OL
V
IH
or V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
-
-
5.5
5.5
6
4.5 to
5.5
-
-
-
-
-
-
100
±0.1
8
±0.5
360
-
-
-
-
±1
80
±5.0
450
-
-
-
-
±1
160
±10
490
µA
µA
µA
µA
Three- State Leakage V
IL
or V
IH
V
O
= V
CC
Current
or GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
∆I
CC
(Note 2)
V
CC
-2.1
2. For dual-supply systems, theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
HCT Input Loading Table
UNIT LOADS
INPUT
D0 - D7
CP
OE
HCT374
0.3
0.9
1.3
HCT574
0.4
0.75
0.6
NOTE: Unit Load is
∆I
CC
limit specific in DC Electrical Specifications
Table, e.g., 360µA max. at 25
o
C.
4
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Prerequisite for Switching Specifications
25
o
C
PARAMETER
HC TYPES
Maximum Clock
Frequency
f
MAX
2
4.5
6
Clock Pulse Width
t
W
2
4.5
6
Setup Time
Data to Clock
t
SU
2
4.5
6
Hold Time
Data to Clock
t
H
2
4.5
6
HCT TYPES
Maximum Clock
Frequency
Clock Pulse Width
Setup Time
Data to Clock
Hold Time
Data to Clock
f
MAX
t
W
t
SU
t
H
4.5
30
-
-
25
-
-
20
-
-
MHz
6
30
35
80
16
14
60
12
10
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
25
29
100
20
17
75
15
13
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
120
24
20
90
18
15
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO 85
o
C
MIN
TYP
MAX
-55
o
C TO 125
o
C
MIN
TYP
MAX
UNITS
4.5
4.5
16
12
-
-
-
-
20
15
-
-
-
-
24
18
-
-
-
-
ns
ns
4.5
5
-
-
5
-
-
5
-
-
ns
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
25
o
C
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO
85
o
C
MIN
MAX
-55
o
C TO
125
o
C
MIN
MAX
UNITS
PARAMETER
HC TYPES
Propagation Delay
Clock to Output
SYMBOL
TEST
CONDITIONS
t
PLH
, t
PHL
C
L
= 50pF
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
-
-
-
-
-
-
-
-
-
-
15
-
-
-
11
-
165
33
-
28
135
27
-
23
-
-
-
-
-
-
-
-
205
41
-
35
170
34
-
29
-
-
-
-
-
-
-
-
250
50
-
43
205
41
-
35
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable to Q
t
PLZ
, t
PHZ
C
L
= 50pF
5
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