CD54HC4075, CD74HC4075,
CD54HCT4075, CD74HCT4075
Data sheet acquired from Harris Semiconductor
SCHS210G
August 1997 - Revised June 2006
High-Speed CMOS Logic
Triple 3-Input OR Gate
Description
The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
Features
• Buffered Inputs
[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
Triple 3-
Input
• Typical Propagation Delay: 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC4075F3A
CD54HC4075FK
CD54HCT4075F3A
CD74HC4075E
CD74HC4075M
CD74HC4075MT
CD74HC4075M96
CD74HC4075NSR
CD74HC4075PW
CD74HC4075PWR
CD74HC4075PWT
CD74HCT4075E
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
20 LCCC
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2006, Texas Instruments Incorporated
1
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Pinout
CD54HC4075, CD54HCT4075 (CERDIP)
CD74HC4075 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4075 (PDIP)
TOP VIEW
2A 1
2B 2
1A 3
1B 4
1C 5
1Y 6
GND 7
14 V
CC
13 3C
12 3B
11 3A
10 3Y
9 2Y
8 2C
SN54HC4075 (FK)
(TOP VIEW)
V
CC
NC
2B
2A
3C
3
1A
NC
1B
NC
1C
4
5
6
7
8
9
1Y
2
1
20
19
18
17
16
15
14
3B
NC
3A
NC
3Y
10
GND
11
NC
12
2C
13
2Y
2
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Functional Diagram
1A
1B
1C
2A
2B
2C
3A
3B
3C
13
3
4
5
1
2
8
11
12
10
3Y
GND = 7
V
CC
= 14
9
2Y
6
1Y
TRUTH TABLE
INPUTS
nA
L
H
X
X
nB
L
X
H
X
nC
L
X
X
H
OUTPUT
nY
L
H
H
H
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant
Logic Diagram
nA
nB
nY
nC
3
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance,
θ
JA
(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113
o
C/W
Maximum Junction Temperature (Hermetic Package or Die) . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
I
I
I
CC
V
CC
or
GND
V
CC
or
GND
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-4
-5.2
0.02
0.02
0.02
4
5.2
-
0
2
4.5
6
4.5
6
2
4.5
6
4.5
6
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
2
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
20
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
40
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
4
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
∆I
CC
(Note 2)
V
CC
and
GND
V
CC
or
GND
V
CC
-2.1
V
OL
V
IH
or V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
V
I
(V)
I
O
(mA)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
V
CC
(V)
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
-
5.5
5.5
4.5 to
5.5
-
-
-
-
100
±0.1
2
360
-
-
-
±1
20
450
-
-
-
±1
40
490
µA
µA
µA
HCT Input Loading Table
INPUT
All
UNIT LOADS
1.6
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical Table, e.g.
360µA max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
TEST
CONDITIONS
25
o
C
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO
85
o
C
MIN
MAX
-55
o
C TO 125
o
C
MIN
MAX
UNITS
PARAMETER
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
SYMBOL
t
PLH,
t
PHL
C
L
= 50pF
2
4.5
6
-
-
-
-
-
-
-
-
-
-
-
8
-
-
-
-
100
20
17
-
75
15
13
10
-
-
-
-
-
-
-
-
125
25
21
-
95
19
16
10
-
-
-
-
-
-
-
-
150
30
26
-
110
22
19
10
ns
ns
ns
ns
ns
ns
ns
pF
C
L
= 15pF
Transition Times (Figure 1)
t
TLH
, t
THL
C
L
= 50pF
5
2
4.5
6
Input Capacitance
C
IN
-
-
5
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