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L-ET1201-L-DT: 产品描述PCI BUS CONTROLLER, PQFP128, LEAD FREE, LQFP-128; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小799KB，共58页; 制造商AVAGO; 官网地址http://www.avagotech.com/

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L-ET1201-L-DT概述

PCI BUS CONTROLLER, PQFP128, LEAD FREE, LQFP-128

L-ET1201-L-DT规格参数

参数名称	属性值
包装说明	LFQFP,
Reach Compliance Code	compliant
Is Samacsys	N
地址总线宽度	32
最大时钟频率	25 MHz
最大数据传输速率	100 MBps
外部数据总线宽度	32
JESD-30 代码	S-PQFP-G128
JESD-609代码	e6
长度	14 mm
端子数量	128
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	250
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压	2.625 V
最小供电电压	2.375 V
标称供电电压	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	TIN BISMUTH
端子形式	GULL WING
端子节距	0.4 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	40
宽度	14 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI
Base Number Matches	1

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Data Sheet

May 5, 2006

ET1201 PCI Fast Ethernet Controller

Features

■

Single chip fast Ethernet network interface control-

lers (NICs) for the PCI bus.

— Low-cost version of ET1201 targeted at PC LAN

on motherboard applications, and low cost NIC

solution.

—

PCI 2.2

specification compliant.

— Provides a direct connection to the PCI bus.

— Support of 10/100 Mbits/s Ethernet communica-

tions.

High performance PCI mastering structure.

— VIA-defined 256 byte I/O-based or memory-

mapped-I/O-based command and status regis-

ters.

— Software oriented chain structure description to

minimize hardware complexity.

— On chip bus master DMA with programmable

burst length for high PCI bus utilization.

— Transmit data buffer byte-alignment for low CPU

utilization.

— Dynamic transmit packet auto-queuing for back-

to-back transmission.

— Programmable activity polling intervals for

description DMA.

— Programmable DMA arbitration priority to mini-

mize overflow under flow conditions.

— Early receive and early transmit interrupts for

software parallel processing.

— Interrupt controllable by receive/transmit.

descriptor list for saving interrupt service time.

— PCI enhance command capable.

Provides standard 10 Base-T/100Base-Tx PHY

layer and transceiver.

— Supports 10Base-T/100Base-TX with CAT5

UTP, and STP.

— 10/100 Mbits/s full-duplex, half-duplex opera-

tion.

— Auto power-saving at cable not link.

— Four LED outputs, including link, duplex, speed,

and collision status.

Separate receive and transmit FIFOs.

— Both support bursts of up to full Ethernet length.

— Programmable receive and transmit FIFO

threshold control for optimize PCI throughput.

Flexible dynamic load EEPROM algorithm.

— Load after power-up.

— Dynamic auto reload.

— Dynamic direct programming for manufacturing.

■

Power management.

— Supports PC99, PC2001, and net PC require-

ments.

— Supports PCI bus power management interface

specification version 1.0/1.1.

— Supports advanced configuration and power

interface (ACPI) specification 1.0.

— Supports network device class power manage-

ment specification version 1.0a.

— Wake-up even support link change/magic

packet/unicast physical address/MS define pat-

tern match.

Flow control.

— Supports

IEEE 802.3X

for full-duplex.

— Multiple pause frame XON/XOFF.

Dual power design: 3.3 V I/O power and 2.5 V core

power.

0.22

µm

TSMC CMOS technology.

128-pin LQFP package.

■

Overview

The ET1201 Ethernet controller is a cutting edge,

feature-rich, and cost-competitive single ASIC chip

solution for PC LAN on motherboard applications or

low cost NIC applications. The ET1201 eases server

processor utilization by optimizing throughput

between the NIC and PCI bus allowing data transfers

of up to at 200 Mbits/s in full-duplex mode, without

using the system CPU. The ET1201 contains

advanced power management features for low power

consumption including wake on LAN (WOL) and is

implemented using a low power 0.22

µm

design.

The ET1201 is ideal for LAN-on-motherboard solu-

tions, providing a manageable, integrated controller

to bring high speed Ethernet connectivity to the elec-

tronics of tomorrow.

■

Agere Systems - Proprietary

ET1201 PCI Fast Ethernet Controller

Data Sheet

May 5, 2006

Table of Contents

Contents

Page

Features .................................................................................................................................................................... 1

Overview.................................................................................................................................................................... 1

Pin Information ..........................................................................................................................................................6

Pin List ...................................................................................................................................................................7

Pin Descriptions .....................................................................................................................................................8

Functional Description .............................................................................................................................................12

Host Bus Interface Control Logic .........................................................................................................................12

Buffer Management .............................................................................................................................................12

FIFO and Control Logic ........................................................................................................................................17

Network Interface .................................................................................................................................................17

EEPROM Interface ..............................................................................................................................................18

Interrupt Control ...................................................................................................................................................20

Flow Control..........................................................................................................................................................20

Power Management............................................................................................................................................. 20

Registers .................................................................................................................................................................22

Register Overview ................................................................................................................................................22

Register Summary ...............................................................................................................................................22

Register Descriptions ...........................................................................................................................................26

Electrical Specifications...........................................................................................................................................51

Absolute Maximum Ratings .................................................................................................................................51

dc specifications ..................................................................................................................................................51

Power Consumption ............................................................................................................................................52

Timing Specifications ...........................................................................................................................................52

Mechanical Specifications .......................................................................................................................................56

Ordering Information................................................................................................................................................57

Figure

Page

Figure 1. Internal Block Diagram ............................................................................................................................. 5

Figure 2. Pin Diagram .............................................................................................................................................. 6

Figure 3. Simple Ring Buffer Structure .................................................................................................................. 13

Figure 4. Receive Descriptor Packet Layout ......................................................................................................... 13

Figure 5. Transmit Descriptor Packet Layout ........................................................................................................ 15

Figure 6. Interrupt Control ..................................................................................................................................... 20

Figure 7. Descriptor Fetch ..................................................................................................................................... 52

Figure 8. Write Back Status to Descriptor ............................................................................................................. 52

Figure 9. Memory Read (Tx FIFO DMA) ............................................................................................................... 53

Figure 10. Memory Write (Rx FIFO DMA) ............................................................................................................. 53

Figure 11. I/O Read/Write ...................................................................................................................................... 53

Figure 12. Configuration Read/Write ..................................................................................................................... 54

Figure 13. LED On/Off (0 < Tpd < 300) ................................................................................................................. 54

Figure 14. 10Base-T Normal Link Pulse Timing (0 < Tpd < 300) .......................................................................... 54

Figure 15. Autonegotiation Fast Link Pulse Timing (0 < Tpd < 300) ..................................................................... 55

Figure 16. Running State Software Driven Internal PHY Reset Timing ................................................................ 55

Figure 17. LQFP-128 Package .............................................................................................................................. 56

Agere Systems - Proprietary

Data Sheet

May 5, 2006

ET1201 PCI Fast Ethernet Controller

Table of Contents

(continued)

Table

Page

Table 1. Pin List (Alphabetical Order) ......................................................................................................................7

Table 2. Pin Descriptions .........................................................................................................................................8

Table 3. Receive Descriptor 0—(RDES0) ..............................................................................................................14

Table 4. Receive Descriptor 1—(RDES1) ..............................................................................................................15

Table 5. Receive Descriptor 2—(RDES2) ..............................................................................................................15

Table 6. Receive Descriptor 3—(RDES3) ..............................................................................................................15

Table 7. Transmit Descriptor 0—(TDES0) .............................................................................................................16

Table 8. Transmit Descriptor 1—(TDES1) .............................................................................................................17

Table 9. Transmit Descriptor 2—(TDES2) .............................................................................................................17

Table 10. Transmit Descriptor 3—(TDES3) ...........................................................................................................17

Table 11. LED Status .............................................................................................................................................18

Table 12. Chip Configuration EEPROM Contents .................................................................................................19

Table 13. Power States ..........................................................................................................................................21

Table 14. PCI Configuration Registers ...................................................................................................................22

Table 15. Internal Registers (00H—FFH) ..............................................................................................................23

Table 16. PHY Registers (00H—1FH) ...................................................................................................................25

Table 17. Offset 1:0—Vendor ID (1106H) RO .......................................................................................................26

Table 18. Offset 3:2—Device ID (3106H) RO ........................................................................................................26

Table 19. Offset 5:4—Command (0006H) RW ......................................................................................................26

Table 20. Offset 7:6—Status (0290H) RWC ..........................................................................................................26

Table 21. Offset 8—Revision ID (nnH) RO ............................................................................................................27

Table 22. Offset B:9—Class Code RO ...................................................................................................................27

Table 23. Offset C—Cache Line Size RW .............................................................................................................27

Table 24. Offset D—Latency Timer RW .................................................................................................................27

Table 25. Offset E—Header Type RO ...................................................................................................................27

Table 26. Offset F—Built In Self Test (BIST) (00h) RO .........................................................................................27

Table 27. Offset 34—Capability Pointer RO ..........................................................................................................27

Table 28. Offset 41—Next Item Pointer RO ...........................................................................................................27

Table 29. Offset 43:42—(Power Management Event) RO .....................................................................................28

Table 30. Offset 4F:44—(Power Management Control Status) RWC ....................................................................28

Table 31. Offset 5:0—(MAC Address) RW ............................................................................................................29

Table 32. Offset 6—(Receive Configure Request) RW ..........................................................................................29

Table 33. Offset 7—(Transmit Configure Request) RW .........................................................................................29

Table 34. Offset 8—(Control 0) RW .......................................................................................................................30

Table 35. Offset 9—(Control 1) RW .......................................................................................................................30

Table 36. Offset 0C—(ISR0) RW ...........................................................................................................................31

Table 37. Offset 0D—(ISR1) RW ...........................................................................................................................31

Table 38. Offset 0E—(Interrupt Mask 0) (00h) RW ................................................................................................31

Table 39. Offset 0F—(Interrupt Mask 1) (00H) RW ...............................................................................................32

Table 40. Offset 17:10—(Multicast Address) RW ..................................................................................................32

Table 41. Offset 1B:18—(Receive Descriptor Base Address) RW ........................................................................32

Table 42. Offset 1F:1C—(Transmit Descriptor Base Address) RW .......................................................................32

Table 43. Offset 6C—(MII Configuration) (MII_CFG) RW ......................................................................................32

Table 44. Offset 6D—(MII Status) (MIISR) RW .....................................................................................................33

Table 45. Offset 6E—(Bus Control 0) (BCR0) RW ................................................................................................33

Table 46. Offset 6F—Bus Control 1 (BCR1) RW ...................................................................................................34

Table 47. Offset 70—MII Control (MIICR) RW .......................................................................................................34

Table 48. Offset 71—Management Interface Address RW ....................................................................................35

Table 49. Offset 73:72—MII Read/Write Data Port RW ..........................................................................................35

Table 50. Offset 74— EEPROM Control/Status (EECSR) RW ..............................................................................35

Table 51. Offset 78—Chip Configuration A (CFG_A) RW .....................................................................................36

Table 52. Offset 79—Chip Configuration B (CFG_B) RW .....................................................................................37

Agere Systems - Proprietary

ET1201 PCI Fast Ethernet Controller

Data Sheet

May 5, 2006

Table of Contents

(continued)

Table

Page

Table 53. Offset 7B—Chip Configuration D (CFG_D) RW .....................................................................................37

Table 54. Offset 80—Miscellaneous Control (CR0) RW ........................................................................................38

Table 55. Offset 81—Miscellaneous Control (CR1) RW ........................................................................................38

Table 56. Offset 82—Power Mgmt Capability Control (PMCC) RO .......................................................................39

Table 57. Offset 83—Sticky Hardware Control (STICKHW) RW ............................................................................39

Table 58. Offset 84—MISC Interrupt Status (MISR) RW .......................................................................................39

Table 59. Offset 86—MISC Interrupt Mask (MIMR) RW ........................................................................................39

Table 60. Offset 98—Flow Control 0 (CR0) RW .....................................................................................................40

Table 61. Offset 99—Flow Control 1 (CR1) RW .....................................................................................................40

Table 62. Offset 9B:9A—(Pause Frame Timer) RW ..............................................................................................40

Table 63. Offset 9D:9C—(Software Timer 0) RW ..................................................................................................40

Table 64. Offset 9F:9E—(Software Timer 1) RW ...................................................................................................40

Table 65. Offset A0/A4—Wake On LAN Set/Clear RW ..........................................................................................41

Table 66. Offset A1/A5—Power Configuration Set/Clear (PWCFG SET/CLR) RW ...............................................41

Table 67. Offset A2/A6—(Wake On LAN Set/Clear) RW .......................................................................................42

Table 68. Offset A3/A7—(WOL Configuration Set/Clear) RW ................................................................................42

Table 69. Offset A8/AC—(Wake-On-LAN Status 0) RWC .....................................................................................43

Table 70. Offset 0—MI Control (3100H) RW ..........................................................................................................44

Table 71. Offset 1—Management Information Status (7849H) RO ........................................................................44

Table 72. Offset 2—PHY Identifier 0 (0101H) RO ..................................................................................................45

Table 73. Offset 3—PHY Identifier 1 (8F43H) RO ..................................................................................................45

Table 74. Offset 4—Autonegotiation Advertisement Base Page (05E1H) RW ......................................................45

Table 75. Offset 5—Autonegotiation Link Partner Base Page Ability (0000H) RO ................................................45

Table 76. Offset 6—Autonegotiation Expansion (0004H) RO ................................................................................46

Table 77. Offset 7—Autonegotiation Advertisement Next Page (2001H) RW ........................................................46

Table 78. Offset 8—Link Partner Advertisement Next Page (0000H) RO ..............................................................46

Table 79. Offset 10H—PHY Configuration 1 (0800H) RW .....................................................................................47

Table 80. Offset 11H—PHY Configuration 2 (F7FFH) RW .................................................................................... 48

Table 81. Offset 12H—PHY Configuration 3 (0800H) RW .....................................................................................48

Table 82. Offset 13H – PHY Interrupt Mask (FFFCH) RW .....................................................................................49

Table 83. Offset 14H—PHY Status (0000H) RO ....................................................................................................50

Table 84. Offset 19H—Power Control RW .............................................................................................................50

Table 85. Absolute Maximum Ratings ....................................................................................................................51

Table 86. dc Specifications .....................................................................................................................................51

Table 87. ET1201 Power Consumption ..................................................................................................................52

Table 88. LED On/Off Timing .................................................................................................................................54

Table 89. 10Base-T Normal Link Pulse Timing ......................................................................................................54

Table 90. Autonegotiation Fast Link Pulse Timing .................................................................................................55

Table 91. Internal PHY Reset Timing .....................................................................................................................55

Agere Systems - Proprietary

L-ET1201-L-DT相似产品对比

	L-ET1201-L-DT
描述	PCI BUS CONTROLLER, PQFP128, LEAD FREE, LQFP-128
包装说明	LFQFP,
Reach Compliance Code	compliant
Is Samacsys	N
地址总线宽度	32
最大时钟频率	25 MHz
最大数据传输速率	100 MBps
外部数据总线宽度	32
JESD-30 代码	S-PQFP-G128
JESD-609代码	e6
长度	14 mm
端子数量	128
最高工作温度	70 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	250
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压	2.625 V
最小供电电压	2.375 V
标称供电电压	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	TIN BISMUTH
端子形式	GULL WING
端子节距	0.4 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	40
宽度	14 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI
Base Number Matches	1

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